Coherent light generators – Particular active media – Semiconductor
Reexamination Certificate
2001-04-12
2003-03-25
Davie, James (Department: 2828)
Coherent light generators
Particular active media
Semiconductor
Reexamination Certificate
active
06539039
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention broadly relates to an optical semiconductor device for use in an optical communication. In particular, this invention relates to an optical semiconductor device of a buried hetero structure type including a semi-insulating semiconductor block layer and a carrier trap layer.
Research and development have been carried out about a variety of optical semiconductor devices as light sources for use in an optical fiber communication system.
Particularly, it is becoming increasingly important to reduce device capacitance in the optical semiconductor device used for high-speed modulation of several G bit/Sec or higher.
Under such circumstance, practical use has been made about a semi-insulating buried hetero structure (hereinafter, may be referred to as a SI-BH structure) having a semi-insulating semiconductor block layer so as to largely reduce the device capacitance and further to effectively achieve a stable lateral mode oscillating characteristic.
Referring to
FIG. 1
, description will be made about a semiconductor laser having the SI-BH structure according to a first related art.
Generally, such a semi-insulating semiconductor block layer serves as a high resistance layer for either of electrons or holes current carriers while it does not serve as the high resistance layer for the other carriers.
To this end, the carrier trap layer is formed for the carriers, which does not serve as the high resistance layer, to enhance current constriction performance (or current narrowing performance).
In the SI-BH structure illustrated in
FIG. 1
, a Fe-doped InP block layer
2
a
is used as the semi-insulating semiconductor block layer. In this event, the Fe-doped InP block layer
2
a
serves as the high resistance layer for the electron current while it does not serve as the high resistance layer for the hole current.
In consequence, an Si-doped InP hole trap layer
3
a
is formed as a hole carrier trap layer at a p-electrode side of the Fe-doped InP block layer
2
a
. With such a structure, the carrier trap layer must be doped with high concentration. Consequently, resistivity is excessively lowered, and an equivalent potential surface is widened with the width of the carrier trap layer so as to increase the device capacitance.
Accordingly, a narrow mesa-structure must be formed by etching to reduce the width of the carrier trap layer in the SI-BH structure having the carrier trap layer.
In the related semiconductor laser illustrated in
FIGS. 1 and 2
, an etching groove reaches the n-InP substrate
1
a
. Consequently, the structure
10
consisting of an electrode
8
b
, an insulating film
7
and the InP substrate
1
a
is formed at the bottom of the etching groove
9
a.
Thereby, an insulating layer thickness as one parameter specifying wiring capacitance is determined by only the thickness of the insulating film
7
. As a result, parasitic capacitance will be
Subsequently, description will be made about another optical semiconductor device according to a second related art with reference to FIG.
3
.
In the related optical semiconductor device, the carrier trap layer
3
a
is entirely severed. Further the semi-insulating semiconductor block layer
2
a
is partially left. Thereby, the structure
10
consisting of the electrode
8
b
, the insulating film
7
, the semi-insulating semiconductor block layer
2
a
, and the n-InP substrate
1
a
is formed such that the insulating layer thickness becomes the total layer thickness of the insulating film
7
and the semi-insulating semiconductor block layer
2
a
. In consequence, the wiring capacitance is reduced in comparison with the related optical semiconductor device illustrated in FIG.
2
.
However, it is necessary to etch the layer having of the thickness of 1.5 to 2 &mgr;m or more including the clad layer in the related structure having the flat buried clad layer
4
c.
Consequently, an etching depth must be controlled at high accuracy to remain the sufficient thickness of the semi-insulating semiconductor block layer
2
a.
More specifically, the thickness of the buried clad layer
4
c
must be set to 3 to 4 &mgr;m or more so as to prevent optical electric field entering into the contact layer
5
a
, the insulating layer
7
, the electrode
8
b
, and the device external portion in an optical semiconductor device having spot-size converter (SSC) waveguide layer.
In consequence, it is required that the etching depth is controlled with excessively high accuracy to remain the sufficient thickness of the semi-insulating semiconductor block layer
2
a.
Further, the etching must be carried out uniformly, and each semiconductor layer must have a uniform thickness.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an optical semiconductor device which has lower device capacitance and is suitable for high-speed transmission and which is capable of manufacturing the optical semiconductor device with excellent repeatability.
According to this invention, an optical semiconductor device is a buried hetero structure type.
With this structure, the optical semiconductor device includes a semi-insulating semiconductor block layer, a carrier trap layer, and a clad layer and a contact layer. Herein, each of the clad layer and the contact layer is formed by selective growth.
Under this circumstance, the carrier trap layer and the semi-insulating block layer have an etched mesa-structure.
In this case, each of the carrier trap layer and the semi-insulating block layer has an etching depth. Further, the semi-insulating block layer is formed on a substrate. Moreover, the etching depth reaches the semi-insulating block layer, and does not reach the substrate.
In this event, the semi-insulating block layer comprises a Fe-doped InP or a Ru-doped InP.
While, the carrier trap layer comprises a Si-doped InP or a Se-doped InP.
More specifically, it is unnecessary to etch the buried clad layer, and only the carrier trap layer is etched according to this invention. In consequence, the controllability of the required etching depth can be largely relieved.
Further, it is possible to accurately remain the semi-insulating semiconductor block layer of the bottom portion of the etching groove to reduce the parasitic capacitance caused by the electrode-wiring pattern.
Thereby, the optical semiconductor device, which has the low device capacitance and is suitable for the high-speed optical transmission, can be manufactured with the excellent repeatability.
Further, a small size optical communication module having the above-mentioned optical semiconductor device can be produced cheaply.
REFERENCES:
patent: 5358898 (1994-10-01), Ogita et al.
patent: 5901265 (1999-05-01), Tohyama et al.
patent: 6229836 (2001-05-01), Okuda
patent: 0 810 462 (1997-12-01), None
Wood-Hi Cheng et al., “High-Speed 1.3 &mgr;m InGaAsP Fabry-Perot Lasers for Digital and Analog Applications,” IEEE Journal of Quantum Electronics, V. 29, 1993, pp. 1660-1667.
Davie James
NEC Corporation
Young & Thompson
LandOfFree
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