Optical communications – Receiver
Reexamination Certificate
1999-12-09
2003-07-22
Chan, Jason (Department: 2733)
Optical communications
Receiver
C398S208000
Reexamination Certificate
active
06595708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an optical receiver circuit used in an optical communication system. More particularly, the invention pertains to an optical receiver circuit suitable for receiving burst digital data, and an optical module using the same in an optical communication system.
2. Description of the Related Art
In general, unlike timewise continuous signal output from video and audio equipment, digital data output from computers typical of information processing equipment has a bursty characteristic, i.e., data is output intensively for a certain period of time and no data is output for the remaining period of time. In an optical communication system for transmitting and receiving such burst data, it is required to provide an optical receiver circuit capable of receiving burst data with high stability.
Referring to
FIG. 1
, there is shown an example of a conventional optical receiver circuit
100
disclosed in Japanese Unexamined Patent Publication. No. 8 (1996)-84160.
FIGS. 2A
to
2
E show waveforms in respective parts of the optical receiver circuit
100
.
Upon receiving an optical signal, a photodetector
1
converts the received optical signal into an electrical signal, which is then supplied to a pre-amplifier
2
. The pre-amplifier
2
amplifies the electrical signal supplied from the photodetector
1
to produce positive and negative signals “a” and “b”.
Under condition that an offset voltage Voff exists in an output of the pre-amplifier
2
, signal levels of the positive and negative signals “a” and “b” in a no-input signal state are “Voff” and “−Voff” respectively, “0” levels thereof in a burst data receiving state are also “Voff” and “−Voff” respectively, and “1” levels thereof in the burst data receiving state are “V+Voff” and “−V−Voff” respectively (FIG.
2
A).
A first peak hold circuit
3
detects a value of a maximum level of the positive signal “a” (hereinafter referred to as a peak value) and generates an output signal “c”, which has a signal level of offset voltage “Voff” in the no-input signal state and a “1” level voltage “V+Voff” in the data receiving state.
A second peak hold circuit
4
detects a peak value of the negative signal “b”, and generates an output signal “d”, which has a signal level of offset voltage “−Voff” in the no-input signal state and a “0” level voltage “−Voff” in the data receiving state (FIG.
2
C).
In
FIG. 1
, resistors
61
to
64
and a differential amplifier
65
constitute an offset canceller
6
. When the output signal “c” of the first peak hold circuit
3
and the negative signal “b” are supplied to a negative input terminal of the differential amplifier
65
through the resistors
61
and
63
having the same resistance value, the levels of the signals “b” and “c” are averaged to provide a signal “f” as a negative input to the differential amplifier
65
. In the signal “f” thus provided, a “0” level voltage in the data receiving state is “V/2”, and a “1” level voltage in the data receiving state and an output voltage in the no-input signal state are zero (FIG.
2
B).
In the same manner as mentioned above, when the positive signal “a” and the output signal “d” of the second peak hold circuit
4
are supplied to a positive input terminal of the differential amplifier
65
through the resistors
62
and
64
having the same resistance value, the levels of the signals “a” and “d” are averaged to provide a signal “e” as a positive input to the differential amplifier
65
. In the signal “e” thus provided, a “0” level voltage in the data receiving state and an output voltage in the no-input signal state are zero, and a “1” level voltage in the data receiving state is “V/2”.
Through the above signal processing, offset voltages “Voff” contained in the signals “a” and “b” output from the pre-amplifier
2
can be canceled mutually. That is, the signals “e” and “f” input to the differential amplifier
65
are subjected to differential amplification on a basis of gain G, thereby outputting a positive signal “g” and a negative signal “h” (FIG.
2
D). These output signals “g” and “h” are not affected by output offset “Voff” of the pre-amplifier
2
, and both the “1” level pulse duty ratio (half value width of pulse per cycle) and the “0” level pulse duty ratio in the signals “g” and “h” are 0.5, i.e. , the signals “g” and “h” are equivalent to each other.
The signal “g” output from the differential amplifier
65
is distinguished as a binary signal in the comparator
7
by comparing with the signal “h”, thereby providing a positive output signal “i”. In the comparator
7
, a binary judgment is carried out to check whether a difference voltage between the signals “g” and “h” is in a positive state or a negative state. In this case, since both the signals “g” and “h” vary symmetrically, the comparator
7
performs the binary judgment with a judgment reference voltage (threshold) which is equivalent to an average value of “1” and “0” levels of the signals “g” and “h”. If the judgment reference voltage in the comparator
7
can be substantially set to an average value of “1” and “0” levels of the signals “g” and “h”, a binary signal “i” having an equal duty ratio may be attained as an output of the comparator
7
regardless of a value of output voltage “V” from the pre-amplifier
2
in the data receiving state.
However, in the circuit configuration shown in
FIG. 1
, the levels of the signals “g” and “h” are equal to each other in the no-input signal state. Consequently, an operation of comparing the signals “g” and “h” in the no-input signal state becomes unstable, making it difficult to attain a correct result in distinction by the comparator
7
. When the pre-amplifier
2
is in the no-input signal state and when the pre-amplifier
2
outputs a “0” level signal of data input, it is required for the comparator
7
to distinguish the input signal “g” as a low level. Hence, for attaining a correct result of binary judgment in the no-input signal state, it is inevitable to use a substantial judgment reference voltage having a value larger than the average value of “1” and “0” levels of the signals “g” and “h”.
If the judgment reference voltage is larger than the average value of “1” and “0” levels of the signals “g” and “h”, however, there arises a problem of deterioration in duty ratio of the output signal “i”.
FIG. 2E
shows a waveform of the output signal “i” having a deteriorated duty ratio. The duty ratio of the output signal “i” varies depending on an amplitude voltage “V” of the positive signal “a”, i.e., a magnitude of the signal output from the photodetector
1
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to obviate the above-mentioned disadvantage of the related art by providing an optical receiver circuit having a duty ratio which does not deteriorate in a burst data receiving state and an optical module containing the optical receiver circuit.
In accomplishing this object of the present invention and according one aspect thereof, there is provided an optical receiver circuit in which a level shift circuit is disposed between a first peak hold circuit for detecting a maximum level of a positive signal and an offset canceller circuit so that an output signal level of the first peak hold circuit is made higher than an actual level for a period of time that an amplitude of a positive signal output from a pre-amplifier is smaller than a predetermined amplitude value.
More specifically, according to the present invention, there is provided a optical receiver circuit comprising: a pre-amplifier for amplifying a signal supplied from a photodetector to output positive and negative signals; a first peak hold circuit for detecting a maximum level of the positive signal output from the pre-amplifier; a second peak hold circuit for detecting a maximum level of the negative signal output from the pre-amplifier; an offset canceller circuit for compensating the positive signal at an output signal level
Bello Agustin
Chan Jason
Kenyon & Kenyon
Opnext Japan, Inc.
LandOfFree
Optical receiver circuit and optical module using same in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Optical receiver circuit and optical module using same in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optical receiver circuit and optical module using same in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3022709