Optical proximity correction method utilizing serifs having...

Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

06670081

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to photolithography, and in particular relates to optical proximity correction methods utilizing serifs, which are variable in size and position, based on the location of the particular serif relative to the surrounding features.
In addition, the present invention relates to a device manufacturing method using a lithographic apparatus comprising:
a radiation system for providing a projection beam of radiation;
a mask table for holding a mask, serving to pattern the projection beam;
a substrate table for holding a substrate;
a projection system for projecting the patterned projection beam onto a target portion of the substrate.
BACKGROUND OF THE INVENTION
Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
These design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or the smallest space between two lines. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
As the critical dimensions of the circuit layout become smaller and approach the resolution value of the exposure tool, the correspondence between the mask pattern and the actual circuit pattern developed on the photoresist layer can be significantly reduced. The degree and amount of differences in the mask and actual circuit patterns depends on the proximity of the circuit features to one another.
Accordingly, pattern transference problems are referred to as “proximity effects.” Proximity effects occur when very closely spaced circuit pattern features are lithographically transferred to a resist layer on a wafer. The light waves of the closely spaced circuit features interact, thereby distorting the final transferred pattern features.
Another common proximity effect problem caused by approaching the resolution limit of the exposure tool is that the corners of the photoresist (both concave and convex) tend to overexpose or underexpose due to a concentration or lack of energy at each of the corners. For example, during exposure to light or radiation the photoresist layer integrates energy contributions from all surrounding areas. Thus, the exposure dose in one vicinity of the wafer is affected by the exposure dose in neighboring vicinities.
Because a corner region in a mask pattern lacks neighboring regions, the exposure dose to a corner of the photoresist layer will always be less than the exposure dose to the main body of the layer. The corners of the developed photoresist pattern, therefore, tend to be rounded, rather than angular, due to the fact that less energy has been delivered to the corners than to the other areas of the masked pattern. In small, dense integrated circuits, such as VLSI circuits, these rounding effects can cause a significant degradation to the circuit's performance. Moreover, rounding results in a loss of contact surface area, which correspondingly reduces the total area available for conduction and accordingly results in an undesirable increase in contact resistance.
To help overcome the significant problem of proximity effects, a number of techniques are used to add sub-lithographic features to mask patterns. Sub-lithographic features have dimensions less than the resolution of the exposure tool, and therefore do not transfer to the photoresist layer. Ins

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Optical proximity correction method utilizing serifs having... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optical proximity correction method utilizing serifs having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optical proximity correction method utilizing serifs having... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3130143

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.