Optical packet switch

Details Optical packet switch Optical packet switch

1999-11-23

2003-01-28

Pascal, Leslie (Department: 2733)

Optical: systems and elements

Deflection using a moving element

Using a periodically moving element

C359S199200, C359S199200, C359S199200, C370S528000

Reexamination Certificate

active

06512616

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an optical packet switch (or switching system) for switching individual packets using an optical switch. More particularly, the invention relates to an optical packet switch in which, without using sophisticated clock synchronizing technology, it is possible to deal with a variation in frame phase due to factors such as skew in an optical switch, thereby making it possible to achieve accurate retiming.
BACKGROUND OF THE INVENTION
Techniques for constructing large-scale packet switches using optical switches are known in the art. However, it is very difficult to perform routing within the switch by referring to packet headers using optical elements alone and to achieve a packet memory using optical elements. For these reasons, packet switches are constructed by combining optical elements with electric circuits. In such a packet switch, the packet switching function is performed by an optical switch and the input/output units of the optical switch are implemented by electric circuits. In an optical switch of the waveguide type, the optical circuit of an optical directional coupler is formed on a substrate made of a GaAs- or InP-compound semiconductor or of a strongly dielectric material such as LiNb03, and the optical path is switched by changing the state of optical coupling by voltage applied to electrodes provided on two closely adjacent optical waveguides. Such an optical switch is capable of high-speed switching on the nanosecond order, by way of example.
FIGS. 8
to
10
are diagrams each illustrating the general structure of an optical packet switch according to the prior art. Each of these optical packet switches employs input and output interface cards composed of electric circuits and an optical switch constituted by optical elements.
For an understanding of the structures of the devices shown in
FIGS. 8
to
10
, refer to the specifications of Japanese Patent KOKAI Publications JP-A-10-123577 and JP-A-6-232897, by way of example.
In the optical packet switch shown in
FIG. 8
, a signal transferred on an optical waveguide
206
selected within an optical switch
205
is a packet-data signal only; no clock signal is transferred. An output interface card
211
has an optoelectronic transducer
208
by which the arriving optical signal transferred through the optical switch
205
is converted to an electric signal, a bit buffer
210
of a transfer terminating circuit
209
in which the electric signal is stored temporarily and read out subsequently as a packet-data signal, and a transmit circuit
219
for outputting a packet-data signal
215
that has thus been retimed.
A problem with the arrangement of this device, however, is how the packet-data signal will be terminated by the clock within the packet of the output interface card
211
. Specifically, with the device shown in
FIG. 8
, a master clock unit
212
within the device distributes a master frame signal
213
to various components in the device (in
FIG. 8
, to a receive circuit
201
in an input interface card
203
and to the transfer terminating circuit
209
in the output interface card
211
). The output interface card
211
performs retiming by generating a clock synchronized to the master frame signal
213
and reading the packet-data signal, which is transferred from the optical switch
205
, out of the bit buffer
210
in response to the generated clock.
If the packet-data signal is a high-speed signal whose frequency is on the gigahertz order or greater, the packet-data signal that enters the output interface card
211
via the optical switch
205
will experience a signal delay or skew that differs depending upon which input interface card it has been transferred from, i.e., depending upon the signal path. It is extremely difficult to define and produce an intra-package clock signal that is capable of being received uniformly by the output interface card
211
regardless of the particular skew. As a result, there is no alternative but to adjust timing by a highly precise adjustment within the device.
In the device illustrated in
FIG. 9
, a burst-receiving PLL (Phase-Locked Loop) circuit
230
regenerates a receive clock signal
217
from the packet-data signal that has been regenerated by the output interface card
211
. The burst-receiving PLL circuit
230
, the input to which is an output signal of an optoelectronic transducer
208
, extracts timing information from the packet data (which is a burst signal) on a packet-by-packet basis and generates the receive clock signal
217
by which the packet-data acceptance timing in the bit buffer
210
is controlled. As a result, the packet-data signal in the output interface card
211
is retimed so that the packets can be accepted.
A problem with the device depicted in
FIG. 9
is that, in the first place, implementing the burst-receiving PLL circuit
230
is difficult. It is particularly difficult to construct a burst-receiving PLL circuit that extracts a clock dynamically packet by packet at high speed on the gigahertz order or greater. Even if such as PLL circuit can be realized it would require too much time to extract the clock. As a consequence, it is impossible to extract a clock and accept data while following up packet transfer on the order of several microseconds or less.
The device shown in
FIG. 10
seeks to avoid the above-described clock adjustment in the output interface card
211
. To accomplish this, wavelengths from a plurality of input interface cards
203
are allocated regularly to all output interface cards
211
and optical signals having these wavelengths are always passed through the optical switch
205
. The output interface card
211
electrically terminates the optical signal of each wavelength from each of the input interface cards
203
and extracts the clock. In other words, a signal always flows on a transfer path from a certain input interface card
203
to the output interface card
211
, and the output interface card
211
performs constant clock extraction individually from signals that are transferred from all of the plurality of input interface cards
203
. This solves the above-mentioned problem associated with dynamic clock extraction and makes it possible to implement arbitrary packet transfer.
Specifically, each output interface card
211
is provided with a receive circuit (DMUX)
230
comprising a plurality of optoelectronic transducers
208
and bit buffers
210
corresponding to respective ones of the plurality of input interface cards (#1 to #N, where N=2 in
FIG. 10
)
203
, and with a selector
220
for selecting any one of the outputs of the DMUX
230
. The wavelengths of the optical signals that are transmitted over the optical waveguides
206
of the optical switch
205
differ for each input interface. In comparison with the arrangement shown in
FIG. 8
, the scale of the electrical receiving circuitry in the output interface card
211
is increased by a factor equivalent to the number (N) of input interface cards, and the scale of the electrical circuitry of the overall device also is increased by a factor of N. This increases the size of the device and raises the cost thereof. In addition, the number of wavelengths of the optical signals transmitted through the optical switch
205
also is N times the number of wavelengths in the arrangements shown in
FIGS. 8 and 9
. The result is an increase in the size and cost of the optical switch
205
.
SUMMARY OF THE DISCLOSURE
Thus, the devices according to the prior art give rise to the following problems:
The first problem is that the device shown in
FIG. 8
is disadvantageous in that it is difficult for the output interface card
211
to retime packet-data signals that are transferred from different input interface cards. The reason for this is that since signal delay or skew is produced that differs depending upon the input interface cards for different sources of transmission, intra-package clock information capable of being received indiscriminately regardless of the particular skew is d

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