Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
2002-01-23
2003-11-25
McPherson, John A. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
C430S325000, C430S326000, C430S396000
Reexamination Certificate
active
06653030
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the manufacture of semiconductors, electrical, electro-mechanical, micro-mechanical, and electro-optical devices that include micron and sub-micron-sized features and, in particular, to a method and system for creating micron and sub-micron-sized features in thin polymer films during layer-by-layer fabrication of micron-feature-containing devices and sub-micron-feature-containing devices.
BACKGROUND OF THE INVENTION
The present invention finds application in the manufacture of many types of modern electronic, electro-magnetic, micro-mechanical, and electro-optical devices that contain tiny, micron and sub-micron-sized elements and components. In the following, such devices are referred to as micro-devices and nano-devices.
One common application of the method and system of the present invention occurs in semiconductor fabrication. During semiconductor fabrication, a semiconductor device is built layer-by-layer on top of a silicon, glass, or polymer substrate. These substrates can be rigid or flexible. Tiny features, such as signal lines and transistors, are fabricated using well-known photolithographic methodologies.
FIGS. 1A-H
illustrate the general method by which micron and sub-micron features are currently fabricated during manufacture of a semiconductor. In
FIG. 1A
, a rectangular section of a silicon substrate
101
is shown. The substrate may be a planarized silicon, glass, or polymer layer, or may be a planarized surface of an already partially fabricated semiconductor. In
FIG. 1B
, an oxide layer
102
is laid down on top of, or grown at the surface of, the substrate
101
. In
FIG. 1C
, a thin photoresist layer
103
is laid down on top of the oxide layer
102
.
A photolithography mask is next placed above the surface of the photoresist, and ultraviolet (“UV”) light is directed through the photolithography mask onto the surface of the photoresist layer
103
. The photolithography mask has transparent regions and opaque regions that define the design of features to be fabricated in the oxide layer
102
below the photoresist layer
103
. The photolithography mask can be either a positive mask or a negative mask, depending on whether the photoresist layer
103
positively or negatively responds to exposure to UV radiation. In the examples shown in
FIGS. 1A-H
, photoresist material exposed to UV radiation is chemically altered, degrading the photoresist and making the photoresist susceptible to dissolution in solvents. The photolithography mask has transparent regions representing features, and UV radiation is blocked from transmission through opaque, non-feature areas of the photolithography mask. Thus, following transmission of UV radiation through the photolithography mask onto the surface of the photoresist layer, areas of the photoresist layer are chemically altered, while non-feature areas remain resistant to dissolution in solvent.
FIG. 1D
illustrates the photoresist layer following transmission of UV radiation through a photolithography mask onto the surface of the photoresist layer. The chemically altered portions of the photoresist
104
and
105
were positioned below transparent regions of the photolithography mask. In a next step, the chemically altered portions of the photoresist layer
103
are removed by exposure of the photoresist layer to a solvent. The removal of the chemically altered photoresist regions leave shallow channels within the photoresist layer, exposing oxide at the bottom of the channels. Next, the oxide layer
102
below the photoresist layer is chemically etched, or etched by a beam of charged particles, to form channels in the polymer layer corresponding to the shallow feature channels in the photoresist. The etching method etches exposed oxide, but is blocked by the remaining photoresist layers that were not chemically degraded by UV exposure. Following etching of the oxide layer, the remaining photoresist is removed by chemical or mechanical processes.
FIG. 1E
shows feature channels etched into the oxide layer by the above-described etching step. The channels
106
and
107
correspond to the feature pattern (
104
and
105
in
FIG. 1B
) created in the photoresist layer by UV radiation exposure. Assuming that the features are metal signal lines, in a next step, a metal layer
108
is deposited onto the surface of the oxide layer
102
, filling the feature channels and adding an additional layer above the oxide layer.
FIG. 1F
illustrates the rectangular portion of the nascent semiconductor device following application of the metal layer. Next, the surface of the nascent semiconductor device is chemically or mechanically planarized to remove the metal layer, leaving metal signal lines embedded within the oxide layer.
FIG. 1G
illustrates the oxide layer with embedded signal lines. Finally, a subsequent polymer, poly-silicon, silicon-oxide, or other type of layer can be laid down on top of the oxide layer for creation of additional features above the features created in the oxide layer
102
. The steps illustrated in
FIGS. 1A-H
can be repeated a number of times to create a complex, three-dimensional array of features within layers of the semiconductor device.
The traditional photolithography-based feature fabrication steps illustrated in
FIGS. 1A-H
have been used for decades to produce ever smaller and more finely detailed semiconductor devices. However, photolithography has numerous deficiencies. A well-known deficiency is the resolution constraints imposed by patterning photoresist layers using UV radiation. Edge-diffraction effects dull the resolution of projected patterns, and edge-diffraction effects become more significant as feature sizes decrease. Another disadvantage of lithography techniques, in general, is that they require many successive, complex steps in order to fabricate features within a particular layer of a semiconductor device. Each step may require careful alignment procedures and expensive and time-consuming chemical, mechanical, vapor-deposition, and charged-particle-beam-based procedures that contribute enormous expense both to creating fabrication facilities as well as to producing finished semiconductor devices. Yet another disadvantage of lithography techniques is that they require a flat surface, so that the entire surface to which patterns of UV radiation are applied remain within a narrow depth of focus. It is thus difficult to apply photolithography techniques to fabricate micron and sub-micron features on inherently difficult-to-planarize surfaces, such as plastic sheets.
In order to overcome the feature-size limitations inherent in photolithographic methodologies, semiconductor manufacturers are developing soft X-ray photolithography methods, and may eventually attempt to employ even shorter-wavelength radiation in order to decrease features sizes to nanometer and sub-nanometer ranges. However, these short-wavelength-radiation techniques are not yet fully commercialized, and are extremely expensive, especially in regard to the capital costs for retooling complex semiconductor manufacturing facilities, mask preparation, and mask/device alignment. However, semiconductor manufacturers are under constant economic pressure to produce smaller and smaller feature sizes, in order to continue to increase the density of microelectronic circuits within semiconductor devices. Moreover, many newer applications for micro-devices and nano-devices are being developed, including complex micro-electromechanical systems, such as sensors and miniature chemical-analysis systems, molecular analysis arrays, electro-optical devices, and other such products of new technologies. Designers, manufacturers, and users of semiconductor devices and other types of micro-devices and nano-devices all recognize the need for micron and sub-micron-feature-fabrication methodologies to economically produce smaller and smaller features and correspondingly increase the density of features within semiconductor devices and other such devices.
SUMMARY OF THE INVENTION
One embodiment
Jeans Albert H
Mei Ping
Taussig Carl P.
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