Dynamic information storage or retrieval – Control of storage or retrieval operation by a control... – Control of information signal processing channel
Reexamination Certificate
1999-04-26
2001-07-10
Tran, Thang V. (Department: 2651)
Dynamic information storage or retrieval
Control of storage or retrieval operation by a control...
Control of information signal processing channel
C369S053320, C369S059260
Reexamination Certificate
active
06259660
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an optical disk apparatus for reproducing data recorded on an optical disk such as a DVD (Digital Versatile Disk) or DVDVRAM or recording data thereon.
Recently, DVDs or DVDRAMs have been developed as an optical recording medium of large capacity. This type of optical disk can be used to record a large amount of data with high density and correctly reproduce recorded data. To serve the purpose, record data and an error correction code used for correcting an error of the recorded data are recorded on the optical disk.
A method for recording data on this type of optical disk is explained with reference to
FIGS. 3A
to
3
D. As is clearly seen from
FIG. 3B
showing the enlarged recording surface of part of an optical disk
10
shown in
FIG. 3A
, a plurality of pits
11
are formed. Sets of the pits
11
constitute sectors as shown in
FIGS. 3C
,
3
D. For example, a track (not shown) is formed in a spiral form from the center towards the periphery on the surface of the optical disk
10
and a sector string formed of a plurality of sectors is formed on the track. The sector string is continuously read by an optical head and recorded data is reproduced on the real time basis.
FIGS. 4A
,
4
B show a sector in which data is recorded. One sector is constructed by 13 rows×2 frames and sync. codes SY
0
, . . . , SY
7
are attached to the frames. The sync. code is used to define a reference timing of a serial/parallel conversion circuit which will be described later. In
FIG. 4B
, the frame arrangement is shown in a 2-dimensional form, but the frames are recorded in order on the track starting from the top frame. That is, if the frames are shown in an order of the sync. codes, the frames are arranged on the track in an order of SY
0
, ST
5
, SY
1
, SY
5
, SY
2
, SY
5
, . . . . The order of each frame can be recognized from the relation between the two continuous sync. codes. The number of bits of the sync. codes constituting one frame is 32 bits (=16 bits×2) and the number of bits of data is 1456 bits (=16 bits×91). The equations in the parentheses indicate that the sync. code and data are 16-bit modulation codes. That is, when data is recorded on the optical disk, 8-bit data is modulated into 16-bit data.
FIG. 5A
shows one decoded sector. In the recording sector, 16-bit data in the above sector is decoded into 8 bits. The data amount in the recording sector is (172+10) bytes×(12+1) rows. In each row, a 10-byte error correction code is added. Further, an error correction code of one row is present in the sector and the error correction code functions as an error correction code for the column direction when 12 rows are obtained as will be described later.
FIG. 5B
shows a data block in which the error correction code is removed from the data of one sector shown in FIG.
5
A. The data block has a sector ID (4 bytes) for identifying a sector, an ID error detection code IED (2 bytes) for detecting an error of the sector ID and copyright management information CPR-MAI (6 bytes) which are attached to the head portion of 2048-byte main data and an error detection code EDC (4 bytes) attached to the end portion of the data.
Next, the error correction code block (ECC block) is explained.
The ECC block shown in
FIGS. 6
,
7
is constructed by
16
sectors having the same construction as described above. However, the sync. code is eliminated. As shown in
FIG. 6
, a 16-byte outer parity (PO) is attached to each column and a 10-byte inner parity (PI) is attached to each row. The outer parity (PO) is error correction data of 172 columns and the inner parity (PI) is error correction data of (192+16) rows. As shown in
FIG. 7
, at the time of recording, the outer parity (PO) of 16 rows shown in
FIG. 6
is arranged in a distributed manner in one sector for each row. As a result, one recording sector is constructed as data of 13 (=12+1) rows. In
FIG. 6
, B
0
,
0
, B
0
,
1
, . . . each indicate an address of byte unit. Further, in
FIG. 7
, numerals
0
to
15
attached to the sectors indicate the numbers of the recording sectors.
FIG. 8
shows the relation between one row of the ECC block shown in FIG.
6
and the frames included in the sector. The ECC block of one row (172 bytes+10 bytes=182 bytes) corresponds to two frames (1456 bits+1456 bits=91 bytes+91 bytes=182 bytes) obtained by eliminating the sync. code in the sector.
FIG. 9
shows a disk apparatus related to this invention. A disk motor
201
drives and rotates an optical disk
202
. An optical head, for example, a laser pickup
203
applies a beam to the pit string on the optical disk
202
to detect the reflected beam by use of a built-in photodiode (not shown) or the like and convert the detected beam into an electrical signal (high-frequency signal: RF signal). An RF amplifier
204
amplifies an RF signal output from the laser pickup
203
and subjects the amplified RF signal to the waveform equalization process. Further, the RF amplifier
204
creates and outputs a focus error signal
205
and tracking error signal
206
. A servo control circuit
207
compensates for the gains and phases of the focus error signal
205
and tracking error signal
206
output from the RF amplifier
204
to drive an actuator (not shown) in the laser pickup
203
. Thus, the stable focus servo and tracking servo can be effected.
A slicer
208
binary-codes an RF signal output from the RF amplifier
204
into a 1-bit digital signal. A data PLL (Phase Locked Loop) circuit
209
reproduces a bit clock signal
210
in synchronism with the RF signal supplied from the slicer
208
. A serial/parallel (S/P: Serial/Parallel) conversion circuit
211
serial/parallel-converts the 1-bit RF signal supplied from the slicer
208
in the unit of 16 bits. As described before, the S/P conversion timing signal is created based on the sync. code in the DVD signal. That is, a sync. code detection circuit
212
detects a sync. code (SY
0
to SY
7
) shown in
FIG. 4B
from the binary-coded RF signal supplied from the slicer
208
. A frame counter
213
counts (32+1456) bits in one frame in synchronism with the sync. code supplied from the sync. code detection circuit
212
. A timing signal generating circuit
214
generates a timing signal for the S/P conversion circuit
211
or the like based on the count of the frame counter
213
. An {fraction (8/16)} demodulation circuit
215
converts a 16-bit code supplied from the S/P conversion circuit
211
into 8-bit data. The converting operation is effected according to conversion data stored in a ROM
216
.
A frame number detection circuit
217
fetches sync. codes of several frames supplied from the sync. code detection circuit
212
and detects the present frame number based on the relation between the preceding and succeeding sync. codes. A frame number counter
219
loads and corrects the frame number supplied from the frame number detection circuit
217
.
An ID detection circuit
220
detects an sector ID provided in the sector unit shown in FIG.
5
B. An address generating circuit
221
generates an address used when data output from the {fraction (8/16)} demodulation circuit
215
is written into a RAM
222
based on the output signal of the frame number counter
219
and the output signal of the ID detection circuit
220
. The 8-bit data output from the {fraction (8/16)} demodulation circuit
215
is supplied to the RAM
222
via a data bus
223
and written into an area corresponding to the address generated from the address generating circuit
221
.
An error correction circuit
224
corrects data stored into the RAM
222
in the unit of inner parity PI and outer parity PO shown in
FIG. 6. A
CPU
225
controls the operation of the whole portion of the optical disk apparatus. An input/output I/F (Inter Face) circuit
226
controls the input/output of data between the RAM
222
and an external device (not shown).
As described before, the sync. codes attached to
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tran Thang V.
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