Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-11-20
2003-09-09
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S448000, C257S459000, C257S503000, C257S773000, C257S784000
Reexamination Certificate
active
06617667
ABSTRACT:
INVENTION FIELD
The invention relates generally to optical devices. In particular, the invention relates to the design of carriers for optical devices.
BACKGROUND
In the electronics and photonics industry, optical components are usually assembled using a number of sub-components, including optical devices such as optical sources and detectors, and carriers for these optical devices. Typically, there are large electrical parasitic capacitances inherent in the carriers, which are structures having conductive patterns as interconnects. The design of the carrier, in particular the layout of the conductive pattern, is one possible reason for the existence of parasitic capacitance.
When an optical component is assembled, an optical device is mounted on and connected to a carrier using a wire bond as interconnect. During high frequency operations, the wire bond becomes predominantly inductive. With the combination of parasitic capacitance due to the layout of the carrier, the inductance in the wire bond and any inherent stray capacitance in the optical device, an LC resonant circuit is inadvertently formed in the optical device. At high frequency operations during which signals are transmitted at high data rates through the optical device, the presence of the LC resonant circuit causes considerable distortion to the signals in the optical device. Hence, design optimization of the carrier is needed to improve the performance.
One example of an optical device is shown in
FIG. 1
, which consists of an optical source such as a laser diode LD mounted on a carrier. The carrier includes a pair of input terminals T
1
and T
2
, and an input-matching resistor RES and a wire bond WB connected in series, the resistor RES and wire bond WB connecting the input terminal T
1
to an input of the laser diode LD. The pair of input terminals T
1
and T
2
provides an interface through which input is provided to the optical device, whereby a signal received at the input terminal T
1
is transmitted first to the resistor RES and then to the laser diode LD, the signal reference of the signal being connected to the optical device ground GND to which the terminal T
2
and a laser diode LD reference is connected. A pair of nodes N
1
and N
2
on the carrier form the physical locations on the layout at which the wire bond WB is connected to the resistor RES and the input of the laser diode LD, respectively. A test pad TP is also connected to the node N
1
for allowing the laser diode LD to be tested for integrity after assembly, in which a parasitic capacitance P_CAP is formed between the connection to the test pad TP and the ground GND. Stray capacitance LD_CAP inherent in the laser diode LD is also formed between both terminals of the laser diode LD.
A conventional layout of the carrier with the laser diode LD mounted thereon is shown in plan and cross sectional side views in
FIGS. 2A and 2B
, respectively. The carrier is structurally based on a substrate SUB and includes the resistor RES and conductors for allowing signal transmission and forming the ground GND for signal referencing. The conductors and resistor RES are etched and laid onto the substrate to form a pattern.
The laser diode LD is mounted on a first ground patch GND
1
which is geometrically shaped like a horizontally mirrored L and patterned on the upper planar surface of the substrate SUB, the size of which is substantially large in relation to the real estate of the carrier so as to provide the laser diode LD with a heat sink for dissipating any heat generated by the laser diode LD. The laser diode LD is also connected to the first ground patch GND
1
at the mounting positions for connecting the laser diode LD reference to the first ground patch GND
1
.
The pair of input terminals T
1
and T
2
is disposed along the edge of the carrier, whereby the input terminal T
1
forms an extremity of an elongated conductor that is connected to the resistor RES at the other extremity. The resistor RES is in turn connected to a conductor patch forming the node N
1
, to which one extremity of the wire bond WB is connected and from which a test pad conductor TPC extends to connect the test pad TP to the node N
1
. The other extremity of the wire bond WB is connected directly to the laser diode LD at the laser diode LD input found on top of the laser diode LD.
The test pad TP is disposed adjacent to the neck and shoulder of the first ground patch GND
1
and the test pad conductor TPC is typically routed close to an edge of the first ground patch GND
1
because this route affords the shortest distance to the test pad TP. By doing this however, the parasitic capacitance P_CAP is formed between the test pad conductor TPC and the first ground patch GND
1
, which inadvertently contributes to the formation of the LC resonant circuit.
The input terminal T
2
is an input ground patch which is connected to a second ground patch GND
2
patterned on the lower planar surface on the substrate SUB through a via V
1
. The second ground patch GND
2
may also be patterned on a different layer in the substrate SUB. The input terminal T
2
is isolated from the first ground patch GND
1
on the upper planar surface of the substrate SUB but is connected to the first ground patch GND
1
through the via V
1
to the second ground patch GND
2
, which in turn is connected to the first ground patch GND
1
through a number of vias V
2
, V
3
and V
4
evenly spaced out on the first ground patch GND
1
.
Frequency responses of the carrier as transmission means obtained both by measurement and software simulation are shown in graphs in FIG.
3
. Both results show a high degree of consistency in that at the operating frequency of 15 GHz, the discrepancy between the insertion losses of the carrier by measurement and simulation is approximately 0.9 dB.
When the laser diode LD is mounted on the carrier, the frequency response of the optical device as transmission means is also obtained and shown as a graph in FIG.
4
. At the operating frequency of 15.5 GHz, the graph shows that there is a resonant peak in the frequency response, which means that signals transmitted through the optical component are distorted when emitted by the laser diode LD. The existence of the resonant peak is a result of the contribution from the parasitic capacitance P_CAP, inductance in the wire bond WB, and the inherent stray capacitance LD_CAP in the laser diode LD.
It is therefore clear from the foregoing that there is a need for conventional designs of optical device carriers to be improved so that insertion loss and resonant peaks at high frequencies may be alleviated.
SUMMARY
In accordance with an aspect of the invention, there is described hereinafter in an optical component having a carrier and an optical device, a layout of the carrier. The layout comprises a pair of terminals, a resistor connected to a first terminal, a wire bond connected in series with the resistor for connecting the resistor to an optical device, and a first ground patch connected to a second terminal and for connecting to an optical device for providing a common ground on a first surface on a substrate on which the carrier is based, whereby the pair of terminals, the resistor, the wire bond and an optical device form an optical signal transmission system in the optical component. In the layout, an optical device is disposable on a first edge of the first ground patch which forms a substantially geometric pattern on the carrier, and the first terminal is connected to the resistor through a conductor which in combination with the resistor forms a first substantially elongated pattern on the carrier that is disposed adjacent and longitudinally orthogonal to the first edge of the first ground patch. Also in the layout, the second terminal is connected to the first ground patch through a conductor that forms a second substantially elongated pattern on the carrier that is spaced apart from and substantially longitudinally parallel to the first substantially elongated pattern, and the second terminal is connected to the first ground patch t
Ishimura Eitaro
Iyer Mahadevan K.
Sakaino Gou
Yeo Mui Seng
Yeo Yong Kee
Conley & Rose, P.C.
Lee Eddie
Mitsubishi Denki & Kabushiki Kaisha
Warren Matthew E.
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