Registers – Coded record sensors – Particular sensor structure
Patent
1986-09-08
1988-05-03
Pitts, Harold I.
Registers
Coded record sensors
Particular sensor structure
235455, G06K 714
Patent
active
047422149
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to an optical card reader capable of optically reading an information signal from each track of an optical card in which information signals are recorded on a plurality of parallel tracks by the arrangement of optically recorded loci such that they can be read optically.
BACKGROUND ART
As a so-called memory card or software card, there is known an optical card 1 in which a plurality of tracks T are formed on a rectangular card substrate in parallel to each other and vertical to its reference end face 1a, as shown in FIG. 1 and information signals are respectively recorded in the respective tracks T by the arrangement of optically recorded loci, for example, pits P as shown in FIG. 2, which can be optically read out.
An optical card reader which reads from such card 1 the information signal recorded on each track T is constructed as shown in FIGS. 3 and 4 such that the card 1 inserted into the reader is transported in the direction shown by an arrow 3 along the reference end face 1a of the card 1 by a card feed roller 2, a light 5 from an irradiating light source 4 such as a light-emission diode is introduced onto the track T of the card 1 through a condenser lens 6, a reflected light from the track T, that is, a reading light 7 of the track T is projected through a focusing lens 8 to a photo detecting element 10 supported on a support plate 9 and the reflected light is detected by this photo detecting element 10. The photo detecting element 10 is constructed just like a line sensor made of a CCD (charge coupled device) such that a plurality of photo detecting elements 10a are arranged rectilinearly and the images projected thereon are read out by the electrical scanning. As shown in FIG. 5, on the photo detecting element 10, the longitudinal direction of the image of the track coincides with the arrangement direction of the detecting elements 10a, whereby images P' of all pits on one track are simultaneously focused on the photo detecting element 10 and thus the informations of one track amount can be read at a time.
The electrical arrangement of the prior art optical card reader is as shown, for example, in FIG. 6. As shown in the figure, the photo detecting element 10 is so formed that a plurality of light receiving elements 10r and transfer elements 10t corresponding to the former one by one are respectively located in opposing relation across a gate 10g.
First, the gate 10g is closed during a predetermined period (accumulation period) so that the charge produced by the light is accumulated in each of the light receiving elements 10r. Then, the gate 10g is opened momentarily to transfer the accumulated charges to the corresponding transfer elements 10t in parallel to one another, respectively. Also, the accumulation of the charges is started again in the light receiving elements 10r. The charges transferred to the respective transfer elements 10t are scanned by a scanning signal (read clock) from a scanning circuit 31 and then read out as a series signal during a constant period (scanning period).
Since the accumulation period and the scanning period are same in time period and timing, the term of the scanning period (scanning) will be used in the following explanation.
The read-out signal, which is the output from the photo detecting element 10, is a discrete analog signal produced at the unit of the detecting element 10a. This signal is amplified to a predetermined level by an amplifier 32 and converted through a sample and hold circuit 33 and a low pass filter 34 to a successive analog signal which is then supplied to a comparator 35. The signal inputted to the comparator 35 is converted to a binary coded signal on the basis of the fact that the voltage thereof is higher than or lower than a reference voltage. The read-out and binary coded signal is supplied to a PLL 36 and a data reproducing circuit 37. In the PLL 36, a clock signal is extracted and then reproduced from the read-out signal and this clock signal is supplied to the data reproducing circuit 37 by which
REFERENCES:
patent: 4101072 (1978-07-01), Weaver
patent: 4267439 (1981-05-01), Thomas
patent: 4507550 (1985-03-01), Fleer
Pitts Harold I.
Sony Corporation
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