Optical bus system and signal processor

Details Optical bus system and signal processor Optical bus system and signal processor

2001-08-30

2003-10-21

Pascal, Leslie (Department: 2633)

Optical communications

Transmitter and receiver system

Including optical circuit board

C398S118000

Reexamination Certificate

active

06634812

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an optical bus system and a signal processor, the optical bus system including an optical bus for transmitting signal light and a light transmitting/receiving circuit for transmitting and receiving signal light, the signal processor performing signal processing including signal light transmission.
2. Description of the Related Art
Along with the development of very large-scale integration (VLSI) circuits has come significantly enhanced functionality of daughter boards used by data processing systems. Because increased circuit functions entail a growing number of signal connections to a given daughter board, data bus boards (mother boards) that interconnect their daughter boards using bus arrangements have come to adopt parallel architectures involving numerous connectors and connection lines. More layers of ever-finer connection lines have been employed to promote parallelism in an attempt to boost the speed at which buses operate. With such architectures, however, system processing speeds are limited by the bus operating speed because of signal delays caused by the capacitance between connection lines and by their resistance. Another problem is the generation of heat by devices consuming more power than before. The monopolization of bus use entails prolonging standby time before signal transmission, which adversely affects system processing speeds. This has given rise to the need for simultaneous signal transmissions between a plurality of daughter boards. A further problem is the presence of electromagnetic interference (EMI) caused by densely arranged bus connection lines. EMI can be a big impediment to improving the speed of system processing.
Increased traffic of communication data has so far been addressed by installing more bus lines because there are limits to the bus operating speed. However, a larger number of bus lines necessitate higher power dissipation, give rise to lower transmission speeds associated with line skew, and take up more line space. Solutions to these disadvantages are proposed in Japanese Published Unexamined Patent Applications Nos. Sho 64-14631 and Hei 8-328707. The cited patent applications disclose analog bus connection schemes intended to reduce the number of lines between devices for easier line arrangements.
FIG. 5
is a schematic block diagram of a typical analog bus connection scheme disclosed in Japanese Published Unexamined Patent Application No. Hei 8-328707.
In
FIG. 5
, devices
501
and
511
are interconnected through an analog bus
506
that connects two A/D converters
504
and
507
as well as two D/A converters
505
and
508
.
An n-bit signal from the device
501
travels over a transmission path
503
to enter the D/A converter
505
for conversion to analog data. The analog data signal is output onto the analog bus
506
to reach the A/D converter
507
for conversion to an n-bit digital signal. The digital signal is input to the device
511
over a transmission path
509
. Conversely, a signal from the device
511
travels over a transmission path
510
to reach the DIA converter
508
for conversion to analog data. The analog data signal is output onto the analog bus
506
to reach the A/D converter
504
for conversion to a digital signal. The digital signal is then input to the device
501
over a transmission path
502
.
As described above, the analog bus
506
in
FIG. 5
functions with multi-level analog signals, while the devices
501
and
511
operate with digital signals.
In the conventional analog bus connection outlined above, the signals that travel over the analog bus
506
are multi-level analog signals. This means that components of bus line resistance and leak currents can cause signal level fluctuations. If bus lines are prolonged in the analog bus or if numerous devices are connected to the bus, it becomes difficult to transmit data correctly.
Many microcomputers require connecting a large number of function blocks using a plurality of buses. Because no communication is available between the multiple buses, it is difficult to implement the above type of analog bus connection scheme. In addressing such difficulties, Japanese Published Unexamined Patent Application No. Hei 8-328707 proposes a circuit to compensate for analog bus level fluctuations. However, the bus lines in the disclosed setup are electrical wires and are thus not fit completely to eliminate the level fluctuations caused by wiring resistance. There still exists the problem of growing power dissipation experienced when attempts are made to drive buses at high speeds, as well as the problem of line skew between parallel lines for mass data transmission. If bus lines are constituted by electrical wires, a multi-logic analog bus structure may be implemented to permit multiplex transmission unidirectionally, but not bidirectionally.
Studies have been made on how to utilize intra-system optical connection techniques called optical interconnection in high-speed signal transmission applications that cannot be implemented using electrical arrangements. Optical interconnection techniques that vary with the system configuration were outlined illustratively by Sadaji Uchida at the 9th Convention of Researchers on Circuit Packaging Technology in Japan (paper 15C0, pp. 201-202); by H. Tomimuro et al., in “Packaging Technology for Optical Interconnects” (IEEE Tokyo, No. 33, pp. 81-86, 1994); and by Osamu Wada in “Electronics” (the April 1993 issue, in Japanese, pp. 52-55).
Of the diverse optical interconnection techniques proposed so far, those disclosed in Japanese Published Unexamined Patent Application No. Hei 2-41042 apply an optical data transmission scheme involving high-speed, high-sensitivity light emitting/receiving devices to a data bus structure. The disclosed setup has the light emitting/receiving devices located on both sides of each of daughter boards installed in a system frame. In the space of the system frame, the light emitting/receiving devices on the contiguous daughter boards are optically connected to form a serial optical data bus for loop transmission between the daughter boards. The scheme works as follows: signal light from a given daughter board is converted to an electrical signal by an adjacent daughter board and then converted back by the same daughter board to signal light before being forwarded to another adjacent daughter board which repeats the same process, and so on. All serially arranged daughter boards in the system frame repeat optical-to-electrical and electrical-to-optical conversion successively for light signal transmission therethrough. The speed of signal transmission is thus dependent on and restricted by the speed of optical-to-electrical and electrical-to-optical signal conversion by the light emitting/receiving devices on each of the configured daughter boards. Because data transmission between adjacent daughter boards is effected through optical coupling in free space between the light emitting/receiving devices on the boards, these devices must be optically aligned and all daughter boards must be optically coupled. Optical coupling in free space can develop cross talk between contiguous optical transmission paths, hereby giving rise to possible data transmission defects. Faulty data transmission is also expected from signal light diffusion caused by ambient conditions (e.g., dust)in the system frame. Since the daughter boards are connected in series, removing any one of them will sever the connection at that point. Any daughter board, if removed, must be replaced by an additional board to preserve the connection. That is, the number of configured daughter boards is fixed and unchangeable.
Japanese Published Unexamined Patent Application No. Sho 61-196210 discloses techniques of data transmission between daughter boards using two-dimensional array devices. The techniques constitute a setup wherein plates with two parallel faces each are positioned opposite to a light source, the plate faces having diffraction grating and

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