Optical arithmetic logic using the modified signed-digit redunda

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350 36, 35016211, 364713, G06F 756, G02B 628, G02B 634, G03H 100

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active

048386464

ABSTRACT:
Optical architectures are presented for performing fully parallel, carry-free computation with a trinary, modified signal-digit number representation to allow addition, subtraction and multiplication. Two different optical schemes involving position and polarization encoding enable the fabrication of modular trinary logic systems that accommodate trinary numbers of different magnitudes. The optical systems made up of redundant three-dimensional modules provide a designer with latitude to simultaneously carry out addition, subtraction or multiplication optically and with reduced complexity.

REFERENCES:
patent: 4351589 (1982-09-01), Chavel et al.
patent: 4386414 (1983-05-01), Case
patent: 4592004 (1986-05-01), Bocker et al.
Simizu et al., "Multi-Layered Iterative Optronic Adder-Subtracter Circuit", em. Fac. Eng. Osaka City Univ. (Japan), vol. 12, Dec. 1971, pp. 47-56.

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