Opposite-phase scheme for peak current reduction

Details Opposite-phase scheme for peak current reduction Opposite-phase scheme for peak current reduction

2011-03-08

2011-03-08

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Layout editor

C716S113000, C716S132000, C716S134000

Reexamination Certificate

active

07904874

ABSTRACT:
We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

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Nieh et al.,Mininmizing Peak Current via Opposite-Phase Clock Tree,Jun. 13-17, 2005, DAC 2005, Anaheim CA, USA, p. 182-185.

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