Amplifiers – With semiconductor amplifying device – Including current mirror amplifier
Reexamination Certificate
2001-11-16
2002-07-02
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including current mirror amplifier
C330S255000, C330S257000
Reexamination Certificate
active
06414552
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to an operational transconductance amplifier, and more particularly, to an operational transconductance amplifier with improved slew rate through the use of a novel, non-linear current mirror.
(2) Description of the Prior Art
Operational amplifiers are a basic building block in many useful electronic circuits. Operational amplifiers provide signal buffer, gain, feedback and signal processing functions in many integrated circuit designs. Designing an operational amplifier requires optimization and tradeoff of several operating parameters. Slew rate, standby or bias current, stability, and frequency response are parameters that are important in a design optimization.
Referring now to
FIG. 1
a typical prior art MOS operational transconductance amplifier circuit is shown. A differential pair is used for the input stage. The differential pair comprises the MOS n-channel, or NMOS, transistors, N
21
22
and N
22
26
. The differential pair is current biased from a single current source implemented as the NMOS device, N
23
30
. N
23
is biased from a bias voltage, V
B
, that establishes a constant current bias, I
B
.
The differential pair N
21
and N
22
gate inputs are coupled to the inverting input, V
IN
−
, and the non-inverting input, V
IN
+
, respectively. The key to operation is that the differential pair will translate differences between the inverting and non-inverting input voltages into differences in the first differential current, I
1
, and the second differential current, I
2
. Neglecting the effect of offset voltage, when V
IN
−
and V
IN
+
are the same voltage, then I
1
=I
2
=I
B
/2. When V
IN
−
exceeds V
IN
+
, then I
1
>I
2
. Conversely, when V
IN
−
is less than V
IN
+
, then I
1
<I
2
. The voltage-to-current (transconductance) conversion gain represented by the differential pair is usually large, often on the order of about 50.
The first differential current, I
1
, is mirrored using the PMOS transistors P
21
34
to P
23
42
. I
1
is then mirrored to from the PMOS device P
23
42
down to the device using N
24
46
. Finally, output device N
25
54
mirrors I
1
to the output signal, V
OUT
, to drive the load, C
L
18
. N
25
54
made be made larger than N
24
46
to multiply the first differential current, I
1
, to create the output current, I
OUTN
. The second differential current, I
2
, is likewise mirrored to the output transistor, P
24
50
, using P
22
38
and may be multiplied to create I
OUTP
.
In the prior art circuit, the output stage is a push-pull configuration output of type Class AB. In this type of output, the signal is driven from the high side, or power supply (V
cc
10
), by an active device and to the low side, or ground
14
, by another active device. Further, when the device is at either rail, that is, the power supply or ground, the output current from the power supply to ground is kept to a minimum since one of the complimentary output devices is OFF.
Referring now to
FIG. 2
, a typical slew rate response for an operational amplifier is shown. The slew rate is a measure of how fast the operational amplifier can switch the output from one rail to the other in response to a step function input. This is a critical parameter in systems, such as switch capacitor circuits, where the amplifier must rapidly drive a large capacitive load. For example, a step function input, V
in
70
, occurs at time=t
o
. A small signal analysis of the operational amplifier circuit shows a predicted response, V
op
74
, to such a step function wherein the output rises exponentially to about V
cc
at time=t
1
. However, the actual measured response is V
oa
78
where the output rises linearly to about V
cc
at the much slower time of t
2
. The reason for the slower response is that the step function represents a large signal change in circuit state that requires the charging and/or discharging of circuit capacitance that must be accomplished using the available bias current. In this case, the operational amplifier is said to be slew rate limited by the available bias current.
To increase the slew rate of the circuit, the bias current may simply be increased. However, in low power applications, the operational amplifier may have a very low budgeted current. In this case, it is not possible to arbitrarily increase the bias current. Prior art approaches to increase the load current-to-bias current ratio, and to thereby increase the slew rate, are stable only over a narrow range of load capacitance. Conversely, operational transconductance amplifiers with dynamic biasing typically have a fixed the load current-to-bias current ratio and are, therefore, not suitable for low current applications.
Several prior art inventions describe operational amplifiers and methods of improving slew rate. U.S. Pat. No. 5,223,753 to Lee et al discloses an operational amplifier having a circuit increase the slew rate without adding to current consumption. An inverted, inverter comprising an NMOS transistor and a PMOS transistor is added between the differential pair stage and the output stage. U.S. Pat. No. 5,515,003 to Kimura teaches a high slew rate operational amplifier where additional transistors gates are coupled to the differential pair gates. During switching, the extra transistors control additional current sources that are coupled in to speed up the slew rate. U.S. Pat. No. 5,883,535 to Kato describes a slew rate controllable amplifier. The current source for the differential pair stage is variable and depends upon the magnitude of the voltage difference between the inverting and non-inverting inputs.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable operational transconductance amplifier.
A further object of the present invention is to provide an operational transconductance amplifier with improved slew rate performance while maintaining a low bias current and excellent stability.
A still further object of the present invention is to provide an improved operational transconductance amplifier by creating an output stage with improved slew rate and low bias current.
Another still further object of the present invention is to provide a non-linear current mirror output stage with a dynamic pole for excellent stability.
In accordance with the objects of this invention, a non-linear current mirror is achieved. The non-linear current mirror is particularly useful in the output stage of an operational transconductance amplifier for improving slew rate and stability while maintaining low bias current. The non-linear current mirror circuit comprises, first, a first MOS transistor having gate, drain, and source. The gate and drain are coupled together and further coupled to a first current input. A second MOS transistor has gate, drain, and source. The gate is coupled to the first MOS transistor gate, and the drain is coupled to a second current input. A third MOS transistor has gate, drain, and source. The drain is coupled to the second MOS transistor source, and the gate is coupled to the second MOS transistor drain. A fourth MOS transistor has gate, drain, and source. The gate is coupled to the third MOS transistor gate. The source is coupled to the first MOS transistor source and the third MOS transistor source. Finally, the drain forms a current output. The current output value linearly tracks the second current input value over a first range of relative values between the first and second current inputs. The current output is a nonlinear, large value over a second range of relative values between the first and second current inputs.
Also in accordance with the objects of the present invention, an operational transconductance amplifier circuit is achieved. The operational transconductance amplifier exhibits improved slew rate and stability while maintaining low bias current. The circuit comprises, first, a differential pair stage having inputs comprising an inverting inp
Kronmueller Frank
Zehnich Paul
Ackerman Stephen B.
Choe Henry
Dialog Semiconductor GmbH
Pascal Robert
Saile George O.
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