Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-06-12
2004-04-27
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S255000
Reexamination Certificate
active
06727753
ABSTRACT:
BACKGROUND
1. Technical Field
An operational transconductance amplifier for an output buffer that improves the current sourcing and sinking drivability for an output load is disclosed.
2. Description of Related Technology
As is well known, an operational amplifier may be connected as a buffer that enables analog signals to be input to the buffer output or driven into greater loads than would otherwise be possible without the buffer.
FIG. 1
is an exemplary circuit diagram that depicts a conventional two-stage operational amplifier that may be used in an output buffer. As shown in
FIG. 1
, the conventional two-stage operational amplifier includes a differential amplification unit
11
, a driving unit
12
and an output load
13
. The differential amplification unit
11
receives a pair of differential input signals (IN+ and IN−) and differentially amplifies the received differential input signals. The driving unit
12
drives the output load
13
connected with an output node N
12
according to the output signals of the differential amplification unit
11
and a bias voltage Vbias.
The differential amplification unit
11
includes a pair of PMOS transistors MP
11
and MP
12
that are used to provide an active load, a pair of NMOS transistors MN
11
and MN
12
, having respective gates to which a pair of differential input signals (IN+ and IN−) are applied and an NMOS transistor MN
13
, to which uniform bias voltage Vbias is applied.
The driving unit
12
includes a PMOS transistor MP
13
that functions as a current source and an NMOS transistor MN
14
for current sinking. A gate terminal of the PMOS transistor MP
13
is connected to an output node N
11
of the differential amplification unit
11
. The transistor MP
13
functions to charge the output load
13
connected to the output node N
12
of operational amplifier. The NMOS transistor MN
14
functions to discharge the output load
13
connected to the output node N
12
using the bias voltage Vbias, which is connected to a gate terminal of the transistor MN
14
. The output load
13
includes a capacitor CL and a resistor RL, both of which are connected to the output node N
12
.
In operation, the differential amplification unit
11
receives a pair of differential input signals (IN+ and IN−) and differentially amplifies the received signals and generates output signals having a predetermined level. When the driving unit
12
sources current to the output load unit
13
, the PMOS transistor MP
13
is turned on in response to a signal provided by the node N
11
of the differential amplification unit
11
, thereby enabling the output load
13
to be charged. On the other hand, to discharge the output load
13
, the PMOS transistor MP
13
is turned off and the NMOS transistor MN
14
is turned on by the bias voltage Vbias.
When considering the current drivability of output load in the conventional two-stage operational amplifier, a drivability of the PMOS transistor MP
13
for sourcing current is typically sufficient to charge the output load
13
. However, the drivability of NMOS transistor MN
14
for sinking current to discharge the output load
13
is typically limited a quiescent current state. Namely, because a fixed bias voltage Vbias is applied to a gate of the NMOS transistor MN
14
to supply bias current to the differential amplification unit
11
, the drivability (i.e., the current drive capability) is much lower than the current source PMOS transistor MP
13
. Thus, to more rapidly discharge the output load unit
13
, the quiescent current of the NMOS transistor MN
14
must be increased. Unfortunately, increasing quiescent current in this manner increases static power consumption of the operational amplifier.
In the case of an LCD source driver for driving each display pixel, an output buffer such as that shown in
FIG. 1
may be used for each pixel. However, the amplifier shown in
FIG. 1
cannot be applied to the LCD source driver due to its excessive power consumption.
FIG. 2
is an exemplary circuit diagram showing a conventional one-stage operational transconductance amplifier. As shown in
FIG. 2
, the conventional one-stage operational transconductance amplifier includes a differential amplification unit
21
, a driving unit
22
and an output load
23
. The differential amplification unit
21
receives a pair of differential input signals (IN+ and IN−) and differentially amplifies the received differential input signals (IN+ and IN−). The driving unit
22
drives the output load
23
, which is connected to an output node N
23
, by a first output signal and a second output signal of a first output node N
21
and a second output node N
22
, respectively, in the differential amplification unit
21
.
The configuration of the differential amplification unit
21
is generally similar to the differential amplification unit
11
shown in FIG.
1
. In
FIG. 1
, the gates of the PMOS transistors MP
11
and MP
12
, which are passive loads, are connected to each other and to a drain of the NMOS transistor MN
11
. On the other hand, in the differential amplification unit
21
shown in
FIG. 2
, the gates of PMOS transistors MP
21
and MP
22
are connected to the drains of NMOS transistors MN
21
and MN
22
, respectively, and the drains form a first output node N
21
and a second output node N
22
, respectively.
The driving unit
22
includes a PMOS transistor MP
24
for sourcing current to charge the output load
23
in response to the second output signal of the second output node N
22
in the differential amplification unit
21
, a PMOS transistor MP
23
and an NMOS transistor MN
24
to supply bias current for current sinking in response to the first output signal of the first output node N
21
in the differential amplification unit
21
and an NMOS transistor MN
25
, which is driven by the current supplied through the PMOS transistor MP
23
and the NMOS transistor MN
24
, for sinking current to discharge the output load
23
. The output load
23
, which is identical to the output load
13
as shown in
FIG. 1
, includes a capacitor (CL) and resistance (RL).
In operation, the differential amplification unit
21
receives a pair of differential input signals (IN+ and IN−) and differentially amplifies the received input signals and then the first and the second output signals are output through the first and second output nodes N
21
and N
22
. To source current to the output load
23
, the PMOS transistor MP
24
is turned on in response to the second output signal outputted through the second output node N
22
in the differential amplification unit
21
.
To sink current from the output load
23
, a current mirror is formed at the PMOS transistor MP
23
, having a gate to which the first output signal of the first output node N
21
in the differential amplification unit
21
is applied, with the PMOS transistor MP
21
in the differential amplification unit
21
and the current flows into the NMOS transistor MN
25
for current sinking through the NMOS transistor MN
24
.
Accordingly, in the conventional one-stage operational transconductance amplifier, as the NMOS transistor MN
25
for sinking current and the PMOS transistor MP
24
for sourcing current are driven in response to the output signals of the first and second output nodes N
21
and N
22
, respectively, the current I/2 flowing through the PMOS transistor MP
24
increases in proportion to the size ratio of the PMOS transistors MP
24
and MP
22
.
Generally speaking, it is advantageous that the drivability for sourcing current and the drivability for sinking current of the output load
23
in the conventional operational transconductance amplifier are identical. However, there is a problem that the maximum driving current of the PMOS transistor MP
24
for sourcing current and the NMOS transistor MN
25
for sinking current of output the load
23
is limited to two times the quiescent state current.
Because the uniform bias voltage Vbias is applied to the gate of the NMOS transistor MN
23
in the differentia
Choe Henry
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
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