Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-08-08
2002-09-24
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
Reexamination Certificate
active
06456162
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and, more particularly, to an operational amplifier that operates at a low supply voltage and has a low offset voltage.
BACKGROUND OF THE INVENTION
For an operational amplifier, low supply voltage refers to a voltage of around 1.8 V. This voltage corresponds to the voltage of two series connected batteries with a nominal voltage of 1.5 volts in a discharged state. In the discharged state, these batteries each have a voltage of around 0.9 volts. An amplifier capable of functioning with a voltage greater than or equal to 1.8 volts optimizes the energy available in battery powered devices. The use of such an amplifier, however, is not limited to battery powered devices.
Operational amplifiers are in various types of electronic circuits, and, in particular, circuits requiring a high current gain. An operational amplifier may be used in interface circuits, power stages, adding circuits, filters, etc. Moreover, operational amplifiers are particularly used in portable devices, such as headphones or mobile telephones, regardless of whether they are being powered by batteries. Moreover, operational amplifiers are particularly used in portable devices, such as headphones or mobile telephones, regardless of whether they are being powered by batteries.
An operational amplifier in accordance with the prior art is illustrated in FIG.
1
. The amplifier has an input stage
100
with first and second input arms
102
a
,
102
b
, which form a differential pair of input arms. The input arms
102
a
,
102
b
each have an input transistor
104
a
,
104
b
respectively connected to input resistors
106
a
,
106
b
. Each input resistor
106
a
and
106
b
is respectively connected between a first supply terminal
1
and the collector of the corresponding input transistor
104
a
,
104
b
. In addition, the emitters of the input transistors are connected in common to a second supply terminal
22
by a biasing current source
108
.
In the example in
FIG. 1
, the input transistors
104
a
,
104
b
are of the pnp type, and the first and second supply terminals
1
,
2
are respectively a ground terminal and a supply terminal that is at a positive potential with respect to ground. The transistors
104
a
,
104
b
have substantially the same characteristics. The bases of the transistors
104
a
,
104
b
form input terminals
100
a
,
110
b
of the operational amplifier. A signal can be applied to the amplifier in the form of a potential difference between the input terminals
110
a
and
110
b
, thus forming a differential input. The potential difference applied between the input terminals has the effect of causing a differential current to flow in the input arms
102
a
and
102
b
. This is defined with respect to an idle state in which no voltage is applied to the input.
A second stage
200
of the amplifier is a level-transforming stage. It has first and second transforming arms
202
a
,
202
b
connected respectively to nodes
103
a
,
103
b
of the input stage. The nodes
103
a
and
103
b
are situated respectively between the input transistors and the input resistors of the first and second input arms
102
a
,
102
b
. The function of the level-transforming stages is to increase the voltage available at the nodes
103
a
and
103
b
so that the input resistors may drive a gain stage with sufficient voltage.
Each transforming arm has respective transistor
204
a
,
204
b
. The bases of these transistors are connected together by a node
205
so that they are commonly set to the same potential. The characteristics of the transistors
204
a
and
204
b
are substantially identical.
In the illustrated example, the transistors
204
a
,
204
b
of the first and second transforming arms are of the npn type and have emitters connected respectively to the nodes
103
a
,
103
b
of the input stage. The collectors of the transistors
204
a
,
204
b
are connected to the second supply terminal
2
by respective current sources
208
a
,
208
b
.
The transforming stage
200
also has a centering arm comprising a centering transistor
207
in series with a centering current source
209
between the first and second supply terminals. The centering current source
209
connects to the first supply terminal
1
the node
205
between the bases of the transistors
204
a
and
204
b
in the transforming arms.
In addition, the centering transistor has a collector connected to the second supply terminal
2
, an emitter connected to the node
205
between the bases of the transistors
202
a
,
202
b
, and a base connected to the collector
203
a
of the transistor
204
a
in the first transforming arm
202
a
. The role of the centering arm is discussed in greater detail below.
A third stage of the amplifier is indicated with reference
300
. This is a current gain stage which connects the level-transforming stage
200
to an output terminal
302
.
A plurality of gain stages can be provided between the level-transforming stage
200
and the output terminal
302
. In this case, the plurality of gain stages forms a gain chain. The input of the gain stage is represented by a transistor
304
whose base is connected to the collector
203
b
of the transistor
204
b
in the second transforming arm
202
b
. The transistor
304
is an npn bipolar type. Its emitter is connected to the first supply terminal
1
and its collector is connected to the second supply terminal
2
by a biasing current source
308
.
The functioning of the amplifier of
FIG. 1
is briefly described below. Considering that the input resistors
106
a
,
106
b
have identical values denoted Re, and considering that the transistors
204
a
and
204
b
in the transforming arms
202
a
and
202
b
have the same transconductance denoted g
m
, it is possible to write:
Δ
I
s
=
g
m
R
E
1
+
g
m
R
E
Δ
I
E
In this equation &Dgr;I
s
indicates a total variation in the current conducted via the transistors in the input arms in response to a potential difference applied between the input terminals
110
a
and
110
b
. &Dgr;I
E
is the variation in the base current of the transistor
304
of the gain stage which results therefrom.
The value of g
m
is such that, where
g
m
=
qI
208
kT
.
The variable I
208
is the (identical) value of the biasing currents delivered respectively by the biasing sources
208
a
,
208
b
in the transforming arms
202
a
,
202
b
, k is Boltzmann's constant, q is the electron charge and T is the temperature.
In the case of an ideal amplifier, the output voltage measured between the supply terminal
1
and the output terminal
302
would become zero when no potential difference is applied between the input terminals
110
a
,
110
b
. However, this is generally not the case because all the components used for building the amplifier, and in particular, the components of the symmetrical arms of the stages, have a variation in their characteristics. This means that the output voltage of the amplifier is not zero in the absence of an input voltage. The state in which no input voltage is applied to the input of the amplifier is also referred to as an idle state in the remainder of the text.
Thus, an offset voltage is defined as being the voltage which must be applied between the input terminals
110
a
,
110
b
so that the output voltage of the amplifier available between the supply terminal
1
and the output terminal
302
is zero. A zero output voltage in the gain stage or gain stages is obtained when the base current, when idle in the transistor
304
at the input of the gain stage, has a given value denoted I
E
. The value I
E
depends on the characteristic of the gain stage or stages.
It is required that the offset voltage should be as low as possible, and preferably zero. As a first approximation, the offset voltage is zero if the currents in the transistors
104
a
and
104
b
in the input arms are identical to each other when idle, and if the currents in the transistor
204
a
,
204
b
in the transfo
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Mottola Steven J.
STMicroelectronics S.A.
LandOfFree
Operational amplifier with offset voltage centering, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Operational amplifier with offset voltage centering, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Operational amplifier with offset voltage centering, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2852904