Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
1999-11-19
2002-04-30
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S257000, C330S261000
Reexamination Certificate
active
06380805
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to circuit design of operational amplifiers (op amps). More in particularly, it relates to reduction of transconductance variation in op amps which use P-channel and N-channel input pairs.
BACKGROUND OF THE INVENTION
Complementary P-channel and N-channel transistor pairs are used often in order to overcome a dead range in the transconductance response of a P-channel input pair or an N-channel input pair alone. A P-channel transistor pair refers to a pair of P-type transistors and an N-channel transistor pair refers to a pair of N-type transistors. In some applications, it is desired to have a response to input EMF (voltage) of an operational amplifier (op amp) which results in a linear variation of output current over a particular voltage range. In order to accomplish this, P-channel and N-channel input pairs of transistors are used. This overcomes a dead range which would result from a threshold voltage if either a P-channel input pair or an N-channel input pair were used alone.
FIG. 1
shows a typical arrangement, in which a pair of P-channel transistors
13
,
14
receive inputs from positive or negative inputs, respectively. A pair of N-channel transistors
17
,
18
, respectively receive the same inputs. The P-channel and N-channel transistors are able to provide discreet outputs, with the transistors receiving the positive inputs providing negative output signals and the transistors receiving negative input signals providing positive output signals. The use of the combination of P-channel and N-channel pairs responding to the same set of input signals overcomes the dead range which would exist if either a P-channel pair or an N-channel pair were used alone. Thus, in the configuration of
FIG. 1
, at an upper voltage range, only the N-channel pair
17
,
18
functions to provide an output, and at a lower voltage range, only the P-channel pair
13
,
14
functions to provide an output. Both pair function at the same time within a middle range. It is desired to make the transconductance value, G
m
of the input pair more stable within the input range.
A very common method of doing this is to permit only one input pair of transistors to work at any given time. In order to accomplish this, a current source transistor
21
is used to provide current to the P-channel pair. If it is desired to turn on the P-channel pair, a low impedance transistor is used to cause all current from the current supply transistor to flow to a lower node. This in turn provides current to drive the end pair. A current mirror is used to connect the lower node to ground, so that either the P-channel pair or the N-channel pair have complementary transistors active at any particular time. Thus, if v
cm
goes low, a control transistor
23
is shut off and the P-channel input pair
17
,
18
become active.
In implementing such an arrangement, the operation of the control transistor
23
is not clear cut. Therefore, a transconductance glitch appears at a transition range of the P-channel input pair and the N-channel input pair. The glitch is a significant current amounting to approximately 25% of the normal G
m
value as shown in FIG.
2
.
SUMMARY OF THE INVENTION
According to the invention, an op amp circuit with complementary pairs of P-channel and N-channel transistors comprising exhibits a reduced transconductance glitch. A first set of complementary P-channel and N-channel transistors receives first and second inputs and is supplied with current through a first power supply and a mirror power supply. At least one additional set of P-channel and N-channel transistors is connected to the first and second inputs and is supplied with current from a second power supply and a second mirror power supply. Control transistors control EMF across the respective sets of P-channel and N-channel transistors and the control transistors interact with the power supplies to establish different transconductance ranges of the sets of P-channel and N-channel transistors. The different transconductance ranges for respective ones of the sets of the P-channel and N-channel transistors causes the op amp to have a reduced transconductance glitch as a result of the different transconductance ranges.
According to a further aspect of the invention, the op amp is configured to provide a predetermined current output, and each set of complementary P-channel and N-channel transistors cooperates in order to provide the predetermined current output. Each set individually provides a proportionally reduced current output, and this permits a reduced current capacity for each of the transistors in said sets. Consequently a correspondingly reducing a layout area is required for fabricating the op amp on an integrated circuit chip. This provides a reduced transconductance glitch as a result of the different transconductance ranges of the respective ones of the sets of the P-channel and N-channel transistors without substantially increasing the layout area.
According to a further aspect of the invention, output fluctuations are reduced during the operation of an op amp which functions with complementary pairs of P-channel and N-channel transistors. First and second sets of complementary P-channel and N-channel transistors are supplied with current through power supply and a mirror power supplies, and are controlled by a first and second control transistors in response to sensed EMF levels. The control transistors each interact with the power supply in order to establish a transconductance range of the P-channel and N-channel transistors at different EMF levels.
According to a further aspect of the invention, different transconductance ranges are used to reduce a transconductance glitch of the op amp by causing the first and second sets of P-channel and N-channel transistors to switch at different times.
According to a further aspect of the invention, an op amp having complementary pairs of P-channel and N-channel transistors is fabricated on an integrated circuit chip, in which output fluctuations during the operation of an op amp are reduced. A determination is made of a desired current output for the op amp to provide and first and second sets of complementary P-channel and N-channel transistors are formed. Respective power supplies and a mirror power supplies are used to control the sets of complementary transistors in response to sensed EMF at different predetermined levels. Sizes of the sets of complementary transistors are determined so that with each set individually provides a proportionally reduced current output, and this permits a corresponding reduction in a layout area for fabricating the op amp.
In the present invention, two sets of complementary P-channel and N-channel pairs of transistors are provided, in which each set is supplied with one half the amount of bias current. In order to control the current going to each set of P-channel and N-channel pairs, a pair of control transistors are used. In one set, the control transistor is a P-type transistor, in which the gate is connected to a supply EMF (voltage). In order that the second set of complimentary pairs have a peak transconductance current at a different voltage, a control transistor for that second set of complementary pairs is provided as an N-type transistor, gated by ground voltage. As a result, the peak in the transconductance current for each of the pairs is reduced at the same time current from the other transconductance pair is provided in a linear fashion. The combined output of the sets of transistors therefore has a much smaller peak in the transconductance range. This peak is nominally half that of what would be accomplished by having a single set of complementary pairs. The use of the P-channel in N-type control transistors also prevents the range of peaks provided by individual transistors from establishing an overlap.
REFERENCES:
patent: 6236269 (2001-05-01), Hojabri
patent: 6242980 (2001-06-01), Tsukagoshi
patent: 6252432 (2001-06-01), Freitas
patent: 6259280 (2001-07-01), Koelling
Bily Stephen F.
Wang Lei
Cirrus Logic Inc.
Murphy James J.
Shingleton Michael B
Winstead Sechrest & Minick
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