Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-07-08
2004-02-24
Nguyen, Long (Department: 2816)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S258000, C330S009000
Reexamination Certificate
active
06696894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of trim circuits, and particularly to trim circuits for operational amplifiers which employ complementary input pairs to achieve a rail-to-rail common mode input range.
2. Description of the Related Art
Operational amplifiers have an associated parameter, referred to as input offset voltage (V
os
), which specifies the op amp's differential input voltage applied to the amplifier's input terminals when the output voltage or current is zero. V
os
is zero for an ideal amplifier. To reduce V
os
, some op amps provide one or more “trim” inputs; applying appropriate currents or voltages to the trim inputs reduces V
os
.
One example of an op amp with a trimmable V
os
is shown in
FIG. 1
; this approach is described in U.S. Pat. No. 6,194,962 to Chen. The op amp's input consists of a first differential transistor pair MN
1
and MN
2
, and a complementary differential transistor pair MP
1
and MP
2
; both input pairs are connected to receive a differential input signal applied to input terminals V+ and V−. MN
1
and MN
2
are biased with a tail current source
10
and MP
1
and MP
2
receive a tail current from a source
12
. In responding to the differential input voltage, each input pair produces a differential current that feeds in to a folded cascode stage
14
, which produces an output current I
out
that varies with the differential currents received from the input pairs. A pair of trim inputs TRIM
1
and TRIM
2
are connected to respective nodes of the folded cascode stage
14
.
In operation, the PMOS input pair (MP
1
, MP
2
) is active when the input common mode voltage (V
cm
) is low (below a pre-set threshold voltage), and the NMOS input pair is active when V
cm
is high (above the pre-set threshold voltage). When a low V
cm
is applied to the op amp, a first correction current &Dgr;I
1
is applied to TRIM
1
or TRIM
2
to reduce V
os
to zero. The correction provided by &Dgr;I
1
is given by &Dgr;I
1
/gmp, where gmp is the transconductance of PMOS transistors MP
1
and MP
2
; correction current &Dgr;I
1
is applied throughout the entire common mode input range. After &Dgr;I
1
has been set, a high V
cm
is applied to the op amp, and a second correction current &Dgr;I
2
is applied to TRIM
1
or TRIM
2
(with &Dgr;I
1
still applied) to reduce V
os
. Thus, for a high V
cm
, the correction provided by &Dgr;I
1
and &Dgr;I
2
is given by (&Dgr;I
1
+AI
2
)/gmn, where gmn is the transconductance of NMOS transistors MN
1
and MN
2
, since &Dgr;I
1
is present throughout the entire common mode input range, while &Dgr;I
2
is only present at high V
cm
.
This approach has several disadvantages. For example, the trim range for a high V
cm
offset has to be larger than the untrimmed offset range, due to the effect of the low V
cm
correction current &Dgr;I
1
. For example, if the untrimmed offset for both high V
cm
and low V
cm
has a range of ±2.5 mV, the trim range for low V
cm
can the be set at ±2.5 mV, but the trim range for a high V
cm
has to be set at ±5 mV. In addition, any supply voltage or V
cm
dependent mismatch of &Dgr;I
1
and &Dgr;I
2
leads to a supply/V
cm
dependence for the post-trim trim V
os
at high V
cm
. This approach also places a constraint on the procedure used to calibrate the op amp, requiring that the calibration be done in a prescribed sequence.
SUMMARY OF THE INVENTION
An operational amplifier is presented which overcomes the problems noted above.
The present op amp provides independent trimming of V
os
for both high and low common mode input voltages. The amplifier includes complementary input pairs, and employs a steering circuit which provides a tail current I
tail
to one input pair when V
cm
is less than a threshold voltage V
th
, and provides I
tail
to the other input pair when V
cm
is greater than V
th
. The input pairs produces an output current I
out
through a load stage; I
out
varies with the pairs' differential output currents. The load stage, which is preferably a folded cascode stage, includes one or more trim inputs which enable V
os
to be varied with one or more trim signals applied to the trim inputs. A first trim signal generating circuit provides a first trim signal to a trim input only when V
cm
is less V
th
, and a second trim signal generating circuit provides a second trim signal to a trim input only when V
cm
is greater than V
th
. This allows the input offset voltages at high and low V
cm
to be adjusted independently, thereby avoiding the problems identified above.
In a preferred embodiment, the steering circuit includes a steering transistor which steers tail current to a PMOS input pair when V
cm
is less than a threshold voltage V
th
, and to a NMOS input pair via a current mirror circuit when V
cm
>V
th
. A first trim signal generating circuit generates a first trim signal, suitable for trimming V
os
at low V
cm
(PMOS pair active), by mirroring a fixed bias current to a first digital-to-analog converter (DAC) which produces the first trim signal in response. A second trim signal generating circuit generates a second trim signal suitable for trimming V
os
at high V
cm
(NMOS pair active) when tail current is steered to the NMOS input pair. A diverting circuit is connected to divert the fixed bias current when tail current is steered to the NMOS input pair, such that the first trim signal is reduced to zero. In this way, the first trim signal can be tailored to trim V
os
at low V
cm
, the second trim signal trims V
os
at high V
cm
, and each trim signal can be independently varied without affecting the other.
REFERENCES:
patent: 6194962 (2001-02-01), Chen
patent: 6522200 (2003-02-01), Siniscalchi
Analog Devices, Precision CMOS single Swupply Rail-to-Rail—Input/Output Wideband Operational Amplifiers, AD8601/AD8602/AD8604, 2000, pp. 1-16.
Analog Devices Inc.
Koppel, Jacobs Patrick & Heybl
Nguyen Long
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