Operational amplifier with increased common mode input range

Details Operational amplifier with increased common mode input range Operational amplifier with increased common mode input range

2003-02-26

2004-06-29

Nguyen, Patricia (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S257000, C330S258000

Reexamination Certificate

active

06756847

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to operational amplifiers, and more particularly, to operational amplifiers with increased common mode input range.
2. Related Art
Standard NTSC color video systems have been commonplace since 1970 and continue to be used widely today. The baseband NTSC video signal is an analog signal with an amplitude of approximately 1.3 Volt-peak-to-peak (V
pp
) and has remained largely unchanged since the technology's inception. Early video systems had relatively large supply voltages where the difference in the positive and negative supply voltage would often be 30 volts. Processing a 1.3 V
pp
signal using analog circuits with 30 V across the supplies means that issues of headroom were rarely a problem. Problems with headroom occur when the input voltage comes too close to the circuit's power supply voltages such that the circuits cannot operate properly. Given a specific supply voltage, a common-mode input range (CMIR) is defined as the range of input voltages over which the circuit can operate correctly.
The desire to integrate many circuits, both analog and digital, onto a single IC means using CMOS technologies with very small geometries. As transistor sizes shrink, more circuits can be integrated using the same amount of silicon area. However, as the transistor size shrinks, so does the maximum voltage across which the devices can safely operate. As the supply voltage approaches the signal amplitude, the challenges in circuit design increase dramatically. The required CMIR may include much of the available supply voltage. Attenuation of the NTSC signal is usually undesirable, because the NTSC signal is single-ended, and such an attenuation will result in a serious noise problem.
Many operational amplifiers (op amps) use rail-to-rail circuit techniques which allows the CMIR to include the entire supply voltage. These topologies often employ two input stages, one for operation near each supply voltage. One input stage will use a PMOS differential pair and the other will use a NMOS differential pair. Because the transconductances of these two input pairs are not matched and will not track each other over process variations, the linearity of the overall amplifier is degraded, and high performance is difficult to achieve.
Another op amp topology often chosen for it's high CMIR is the folded-cascode topology (See “Analysis and Design of Analog Integrated Circuits”, Gray, Hurst, Lewis & Meyer, John Wiley and Sons, 4
th
ed. 2001, pp. 446-450). Defining the MOS threshold voltage as V
t
and the overdrive voltage V
GT
=V
GS
−V
t
, in FIG. 6.28 of Gray et al., maximum input common-mode voltage V
CMI
(max)=V
DD
−V
t5
−V
GT5
−V
GT1
(assume matched transistor pairs M
1
-M
2
, M
11
-M
12
, M
1
A-M
2
A in FIG. 6.28 of Grey et al., with the numeric subscript referring to the transistor number). Also the V
t
's and V
GT
's are assumed to be positive whether the transistor is NMOS or PMOS. Voltages greater than V
CMI
(max) will cause M
5
to leave saturation and it's current will drop. The folded-cascode circuit often allows the V
CMI
to reach the negative supply, usually ground in low supply voltage circuits, without any problems. However, in unity gain buffer configurations, where the inverting op amp input is tied to the output, it is the output which will limit the voltage swing.
Although the linearity of the folded-cascode op amp is better than the typical rail-to-rail designs, it still has linearity problems due to the finite output impedance of M
5
in FIG. 6.28 of Gray et al. As the common mode input voltage V
CMI
changes, the tail current I
D5
will change, which will in turn change the gain of the stage. The stage gain varies as a function of the input stage transconductance g
m
times the output resistance R
0
. The gain goes down as the tail current increases. To overcome this problem, the tail current source could be cascoded, however this would further reduce V
CMI
(max) by an additional V
GT
term.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an operational amplifier with increased common mode input range that substantially obviates, one or more of the disadvantages of the related art.
There is provided an operational amplifier including a first stage with a first differential transistor pair receiving a differential input signal at their gates, a first tail current source transistor connected to sources of the first differential transistor pair, and a load transistor pair connected in series with drains of the first differential transistor pair. An input stage includes a second differential transistor pair connected to respective drains of the first differential transistor pair at their gates, and a second tail current transistor connected to sources of the differential transistor pair. An output stage outputs a signal corresponding to the differential input signal.
In another aspect there is provided an operational amplifier including a first stage inputting a differential input signal. An input stage includes a second differential transistor pair connected to the first stage, and a tail current transistor connected to sources of the differential transistor pair. An output stage outputs a signal corresponding to the differential input signal. The first stage expands a common mode input range of the input stage.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4345213 (1982-08-01), Schade, Jr.
patent: 5808513 (1998-09-01), Archer
patent: 6559720 (2003-05-01), Huijsing et al.
patent: 6563381 (2003-05-01), Strong
patent: 6657486 (2003-12-01), Kimura
Paul R. Gray et al.,Analysis and Design of Analog Integrated Circuits, 4thEdition, 2001, pp. 446-450.

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