Amplifiers – With plural amplifier channels – Redundant amplifier circuits
Reexamination Certificate
2000-09-01
2003-07-08
Shingleton, Michael B (Department: 2817)
Amplifiers
With plural amplifier channels
Redundant amplifier circuits
C330S051000, C330S069000, C330S107000, C330S109000, C330S12400D, C330S295000, C257S207000, C257S919000
Reexamination Certificate
active
06590448
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an operational amplifier topology for use in integrated circuits. More particularly, the present invention relates to a method and circuit for providing an operational amplifier having selectively configurable input and output characteristics to optimize the performance of the operational amplifier.
BACKGROUND OF THE INVENTION
The demand for less expensive, and yet more reliable integrated circuit components for use in communication, imaging and high-quality video applications continues to increase rapidly. Integrated circuits have generally been comprised of two classes of products, merchant parts and custom layouts for products. The integrated circuit industry generally manufactures merchant parts in high volumes, and sells such products in competitive wide-application markets.
In addition to the merchant parts, the integrated circuit industry has also long provided integrated circuits for which “custom” integrated circuit mask layouts have been generated for each chip. However, these custom integrated circuits are relatively more expensive to design, layout and manufacture in that the integrated circuits are generally sold in lower volumes. For instance, the layout topography, i.e., the three-dimensional, layered configuration which embodies the miniature electronic circuits of an integrated circuit, has been painstakingly laid out to achieve multiple objectives in a custom layout. One objective includes the minimization of the chip size, i.e., the layout is designed to minimize the total dice area to the extent reasonably feasible. In addition to creating a full set of masks for these products, a full custom integrated circuit is typically designed component by component in a fashion analogous to the laying out of discrete components on printed circuit boards (PCBs). Thus, the layout topography is designed to facilitate the mounting of the completed integrated circuit chip into a predetermined package with a predetermined number of leads and lead locations. Further, the entire interconnect pattern must be developed within the layout topography to minimize interconnect conductor lengths which have parasitic capacities associated therewith and thus, to minimize cross-talk and various other detrimental parasitic effects.
Due to the above costs considerations in design and layout, cell-based application specific integrated circuits (ASICs) have been developed. In these applications, a large number of various standard integrated circuit “cells” can be formed on an integrated custom layer. These cell-based ASICs are generally designed with at least one dimension, e.g., the height, common to all the cells, and with the cells configured in rows similar to an array. As a result, very rapid, low cost design of a chip for a specific application can be realized. Such standard cells include various two-stage operational amplifier cells and three-stage operational amplifier cells.
With reference to
FIG. 1
, a prior art two-stage operational amplifier (op amp)
100
, which can be a “standard cell” in a library of integrated circuit cells is illustrated. Two-stage op amp cell
100
is generally formed by retrieving in digital form, and strategically placing in an integrated circuit mask layout as part of the overall layout of an integrated circuit chip. Two-stage op amp cell
100
includes two amplifiers
102
and
106
, which can be referred to as transconductance stages or g
m
stages, such as an input g
m
stage
102
and an output g
m
stage
106
. In operation, input voltages V
in
+
and V
in
−
are suitably applied through conductors
103
and
104
to the negative (−) and positive (+) inputs, respectively, of input g
m
stage
102
. The output of g
m
stage
102
is suitably connected by an internal node
105
to the negative (−) input of output g
m
stage
106
, with the positive (+) input of the output g
m
stage
106
being connected to ground. The term “internal node” as used with reference to node
105
refers to a node that would saturate due to mismatches between input transistors and/or other components if multiple op amp cells were to be connected in parallel by bussing, i.e., connecting together, their corresponding input and output terminals together. In addition, output g
m
stage
106
includes an output
107
which is coupled through a compensation capacitor C
COMP
108
in a feedback arrangement to internal node
105
.
The use of a single two-stage amplifier is limited to a few applications due to limitations in power and its use at high frequencies. To overcome these power limitations, some techniques have attempted to provide for a parallel connection of a plurality of solid state amplifier elements, which each element sharing a portion of the amplification task. Theoretically, the total output power for such a configuration is equal to the product of the number of amplifier elements used and the power output of a single element.
Due to the above mentioned internal node saturation problem, it has been difficult and impractical to construct larger operational amplifiers by connecting a number of standard op amp cells in parallel simply by bussing their corresponding input terminals together and their corresponding output terminals together. Accordingly, while amplifier inputs have been bussed together in some applications, these connections generally have not been conducted within a single integrated circuit chip, but have utilized amplifier devices from several chips. In addition, such applications have required summing resistors, transformers, or other impedances, to connect the inputs or the outputs of the g
m
stages to the summing conductors. These resistors are generally configured within the bussing connections to absorb power resulting from mismatching of input and output components that are connected together. However, the use of summing resistors is impractical in an integrated circuit implementation because low resistance summing resistors require a great deal of chip area and hence are overly expensive to manufacture.
In another approach, some applications have comprised an ASIC methodology wherein in the maximum number of amplifier cells needed for any application would be configured in a custom layout, with multiple types of op amp cells incorporated to meet the required performance. For example, a quad operational amplifier layout has been utilized for providing a single or dual version of the same product. However, while the inclusion of the maximum number of op amp cells can address many of the performance needs, numerous op amp cells are not used in many applications, i.e., the unused op amp cells are not reconfigured for optimum performance.
Accordingly, a need exists for an operational amplifier topology that can facilitate the optimization of the input, output and layout characteristics of an operational amplifier. In addition, a need exists for an operational amplifier topology for facilitating the layout of operational amplifiers having various input and output characteristics that are readily configurable, rather than requiring a custom layout which needs the resizing of the input or output stages to meet a particular design performance criteria.
SUMMARY OF THE INVENTION
The method and circuit according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a technique is provided which facilitates the layout of op amp cells, for example, two-stage op amp cells or three-stage op amp cells, to provide larger operational amplifiers. In accordance with one aspect, the op amp cells can be suitably coupled in parallel to provide a larger operational amplifier. This paralleling aspect may be facilitated by connecting the respective negative and positive inputs of a predetermined number of input g
m
stages together, connecting the outputs of a predetermined number of output g
m
stages together, and connecting a predetermined number of intermediate internal nodes between the i
Brady W. James
Shingleton Michael B
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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