Operational amplifier circuit including folded cascode circuit

Details Operational amplifier circuit including folded cascode circuit Operational amplifier circuit including folded cascode circuit

1999-12-15

2001-05-22

Mottola, Steven J. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S255000, C330S257000

Reexamination Certificate

active

06236270

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an operational amplifier circuit, and more particularly to an operational amplifier circuit including a folded cascode circuit, suitable for application to semiconductor integrated circuits.
2. Description of the Related Art
FIG. 2
is a circuit diagram showing an example of the electrical configuration of a conventional operational amplifier circuit.
This example of the operational amplifier circuit represents the one disclosed in IEEE Journal of Solid-State Circuits, Vol. SC-19, p. 920, 1984. The circuit is mainly composed of P-channel MOS transistors (referred to as PMOSs hereinafter)
1
to
8
, N-channel MOS transistors (referred to as NMOSs hereinafter)
9
to
14
, and a capacitor
15
.
The PMOSs
1
and
2
constitute a differential transistor pair in which input voltages V
IN1
, and V
IN2
are applied to their respective gates, and their respective source electrodes are connected in common to the drain electrode of the PMOS
3
. The drain electrode of the PMOS
1
is connected to the source electrode of the NMOS
10
, and the drain electrode of the PMOS
2
is connected to the source electrode of the NMOS
11
. The PMOS
3
receives a first power supply voltage V
1
to its source electrode and receives a reference bias voltage V
B11
to its gate electrode, and constitutes a constant current source.
The PMOS
4
receives the first power supply voltage V
1
to its source electrode and receives the reference bias voltage V
B11
to its gate electrode to form a constant current source, and has its drain electrode connected to the source electrode of the PMOS
5
. The PMOS
5
receives an input voltage V
IN2
to its gate electrode, and constitutes an input transistor pair together with the PMOS
2
. The drain electrode of the PMOS
5
is connected to the drain electrode and the gate electrode of the NMOS
9
. The NMOS
9
receives a second power supply voltage V
2
to its source electrode, and its gate electrode and drain electrode are connected to the gates of NMOSs
12
and
13
to constitute a constant current source. The PMOSs
6
and
7
constitute a current mirror in which an equal amount of current is made to flow in each transistor, receive the first power supply voltage V
1
to respective source electrodes, have respective gate electrodes connected to the drain electrode of the PMOS
6
, and receive a reference voltage V
REF
to the connection point. Moreover, the gate electrode and the drain electrode of the PMOS
6
are connected to the drain electrode of the NMOS
10
, and the drain electrode of the PMOS
7
is connected to the drain electrode of the NMOS
11
. The gate electrodes of the NMOSs
10
and
11
are interconnected, and receive a reference bias voltage V12. The NMOSs
12
and
13
constitute a constant current source, where respective source electrodes receive the second power supply voltage V
2
, the drain electrode of the NMOS
12
is connected to the source electrode of the NMOS
10
, and the drain electrode of the NMOS
13
is connected to the source electrode of the NMOS
11
. The PMOSs
1
and
2
, and the NMOSs
10
and
11
constitute a folded cascode stage, and an output voltage V
FCOUT
of the folded cascode stage is taken out from the drain electrode of the NMOS
11
.
The PMOS
8
is an output transistor, where its source electrode receives the first power supply voltage V
1
, its gate electrode is connected to the drain electrode of the NMOS
11
, and its drain electrode is connected to the drain electrode of the NMOS
14
. The NMOS
14
is a constant current load, its gate electrode receives a reference bias voltage V
B13
, and its source electrode receives the second power supply voltage V
2
. The PMOS
8
and the NMOS
14
constitute an inverting amplifier which amplifies the output voltage V
FCOUT
of the folded cascode stage by inverting it, and outputs the result from the drain electrode of the PMOS
8
as an output voltage V
OUT
. The capacitor
15
is for phase compensation, and has its one end connected to the source electrode of the NMOS
11
, and the other end connected to the drain electrode of the PMOS
8
.
With such a configuration, it is possible to realize a current supply type operational amplifier which has a high gain and a wide bandwidth.
Now, the conventional operational amplifier circuit described above has an input stage that consists of the PMOSs
1
,
2
, and
5
so that it has a low input impedance and is of a low potential input type. Accordingly, the circuit is not applicable to a circuit, such as an interface part of a data transmission/reception circuit, which requires a high potential input because of the normally high potential output of a circuit connected in the preceding stage.
For this reason, it is necessary to constitute the input stage using NMOSs which have high input impedances. In that case, if a PMOS (PMOS
8
in
FIG. 2
) with a large gate electrode width continues to be employed for the output stage in order to enhance the current supply capability to meet the requirement that the operational amplifier circuit be of a current supply type, then the output voltage V
OUT
is affected by the variations in the power supply and the dispersion in the threshold voltage V
t
of the output stage PMOS, which gives rise to a problem that the offset between the input voltages V
IN1
, V
IN2
and the output voltage V
OUT
is large. Namely, if the threshold voltage V
t
of the output stage PMOS is low, the output current of the output stage PMOS becomes large, and if the threshold voltage V
t
of the output stage PMOS is high, the output current of the output stage PMOS becomes small, and these variations show themselves up as the variations in the output voltage V
OUT
, which makes the offset large.
In this connection, if the input stage is constituted of PMOSs, the dispersion of the threshold voltage V
t
of one (PMOS
7
in
FIG. 2
) of the PMOSs constituting the current mirror connected to the folded cascode stage and the dispersion of the threshold voltage V
t
of the PMOS (PMOS
8
in
FIG. 2
) have the same direction, so that they cancel each other, and the offset can be suppressed.
With this constitution, however, it is impossible to realize a high potential input because the input stage is formed of PMOSs.
SUMMARY OF THE INVENTION
It is therefore the object of the present invention to provide a current supply type operational amplifier circuit which has a high gain and a wide bandwidth, is of a high potential input type and is capable of suppressing the input/output offset.
An operational amplifier circuit of the present invention comprises a first transistor of a first conductivity type having a first control gate supplied with a first input voltage and a first current path coupled between a first node and a second node; a second transistor of the first conductivity type having a second control gate supplied with a second input voltage and a second current path coupled between the first node and a third node; a third transistor of a second conductivity type having a third control gate and a third current path coupled between the third node and a fourth node; a fourth transistor of the second conductivity type having a fourth control gate coupled to the third control gate and a fourth current path coupled between the second node and a fifth node; a fifth transistor of the first conductivity type having a fifth control gate and a fifth current path coupled between the fourth node and a sixth node; a sixth transistor of the first conductive type having a sixth control gate coupled to the fifth control gate and having a sixth current path coupled between the fifth node and seventh node; a current mirror circuit having an input node coupled to the sixth node and an output node coupled to the seventh node; and a seventh transistor of the second conductive type having a seventh control gate coupled to the seventh node.


REFERENCES:
patent: 4963834 (1990-10-01), Yukawa
Ribner, et al., “Design Techniques for Cascoded CMOS

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