Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-02-28
2006-02-28
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C330S282000
Reexamination Certificate
active
07006070
ABSTRACT:
An output of an operational amplifier circuit is set to the high impedance state in a given period including a transition between a period T1(positive polarity) in which a voltage level of a counter electrode VCOM becomes VC1and a period T2(negative polarity) in which VCOM becomes VC2. In the period T1, data line is driven by a P-type operational amplifier OP1having a P-type driving transistor, while in the period T2, the data line is driven by an N-type operational amplifier OP2having an N-type driving transistor. By positively using a parasitic capacitance between the counter electrode and the data line, the voltage level of the data line is changed before driving. The excess charge is returned to the power source side by clamping the output of the operational amplifier circuit to a voltage range equal to or wider than a voltage range of power sources VDD and VSS. The voltage range of power sources VDD′ and VSS′ of a clamp circuit are set to be narrower than that of the power sources VDD and VSS of the operational amplifier circuit.
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Dinh Duc Q
Liang Regina
Oliff & Berridg,e PLC
Seiko Epson Corporation
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