Operational amplifier

Amplifiers – With semiconductor amplifying device – Including differential amplifier

Reexamination Certificate

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C330S263000, C330S255000

Reexamination Certificate

active

06806770

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2002-122154, filed on Apr. 24, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to an operational amplifier that uses a bipolar transistor in an output circuit.
Nowadays, semiconductor devices used in various types of electronic equipment are required to have a lower power supply voltage and lower power consumption. Thus, the output voltage of an operational amplifier mounted on a semiconductor device tends to decrease. Accordingly, an operational amplifier that functions under a lower power supply voltage without decreasing its output voltage is required.
FIG. 1
is a schematic circuit diagram of an operational amplifier (hereafter, referred to as op amp)
50
in the prior art. The op amp
50
has a pure complementary output circuit, which includes an NPN source output transistor Tr
9
and a PNP sink output transistor Tr
7
. The op amp
50
uses a bipolar transistor to achieve the required temperature characteristics and large output current and to guarantee reliability in the manufacturing process.
The base of a PNP transistor Tr
1
receives an input voltage IN1, and the collector of the PNP transistor Tr
1
is connected to the collector of an NPN transistor Tr
3
. The base of a PNP transistor Tr
2
receives an input voltage IN2, and the collector of the PNP transistor Tr
2
is connected to the collector of an NPN transistor Tr
4
. The NPN transistors Tr
3
and Tr
4
configure a current mirror circuit. The emitters of the transistors Tr
1
and Tr
2
are connected to a common power supply
1
.
The power supply
1
supplies the transistors Tr
1
and Tr
2
with a constant current in accordance with a power supply Vcc. The bases of the transistors Tr
3
and TR
4
are connected to the collector of the transistor Tr
4
. The emitters of the transistors Tr
3
and tr
4
are connected to the ground GND.
The collectors of the transistors Tr
1
and Tr
3
are connected to the base of an NPN transistor Tr
5
. The emitter of the transistor Tr
5
is connected to the ground GND. The collector of the transistor Tr
5
is connected to the bases of PNP transistors Tr
6
and Tr
7
and to the collector of the transistor Tr
6
. The transistors Tr
6
and Tr
7
configure a current mirror circuit.
The emitter of the transistor Tr
6
is connected to the emitter of an NPN transistor Tr
8
. The emitter of the NPN transistor Tr
7
is connected to the emitter of an NPN transistor Tr
9
. The bases of the transistors Tr
8
and Tr
9
and the collector of the transistor Tr
8
are connected to a current source
2
. The current source
2
generates constant current in accordance with the power supply Vcc. The collector of the transistor Tr
9
is connected to the power supply Vcc. An output signal Vout is generated at the emitters of the transistors Tr
9
and Tr
7
.
In the op amp
50
, when the input voltage IN2 is greater than the input voltage IN1, the collector current of the transistor Tr
2
decreases, and the base current of the transistors Tr
3
and Tr
4
decreases. This decreases the collector current of the transistors Tr
3
and Tr
4
.
Since the collector current of the transistor Tr
1
does not change, the base current of the transistor Tr
5
increases. As a result, the collector current of the transistors Tr
6
and Tr
7
increases. The base current of the transistors Tr
8
and Tr
9
are constant in accordance with the current source
2
. Thus, the collector current of the transistors Tr
8
and Tr
9
is constant. Accordingly, the output voltage Vout decreases.
When the input voltage IN2 is less than the input voltage IN1, the collector current of the transistor Tr
2
increases, and the base current of the transistors Tr
3
and Tr
4
increases. This increases the collector current of the transistors Tr
3
and Tr
4
.
Since the collector current of the transistor Tr
1
does not change, the base current of the transistor Tr
5
decreases. As a result, the collector current of the transistors Tr
6
and Tr
7
decreases. The base current of the transistors Tr
8
and Tr
9
is constant in accordance with the current source
2
. Thus, the collector current of the transistors Tr
8
and Tr
9
is constant. Accordingly, the output voltage Vout increases.
In the op amp
50
, the idling current of the transistors Tr
9
and Tr
7
may be set at a small value with the current source
2
. However, in the op amp
50
, the maximum output voltage VoutH is less than the power supply Vcc by at least an amount corresponding to the base-emitter voltage drop VBE. The minimum output voltage VoutL is greater than the power supply Vcc by at least an amount corresponding to the base-emitter voltage drop VBE. Accordingly, when decreasing the amplitude of the output voltage Vout to decrease the power supply voltage, the amplitude of the output voltage is insufficient.
The transistor Tr
5
is arranged between the transistors Tr
1
, Tr
2
and the transistors Tr
9
, Tr
7
. This decreases the response speed of the output voltage Vout relative to the input voltages IN1 and IN2.
FIG. 2
illustrates another op amp
50
A in the prior art. Output transistors Tr
16
and Tr
18
are both NPN transistors. The op amp
50
A includes a sub-complementary output circuit.
The base of a PNP transistor Tr
11
receives an input voltage IN3, and the collector of the PNP transistor Tr
11
is connected to the collector of an NPN transistor Tr
13
. The base of a PNP transistor Tr
12
receives an input voltage IN4, and the collector of the PNP transistor Tr
12
is connected to the collector of an NPN transistor Tr
14
. The NPN transistors Tr
13
and Tr
14
configure a current mirror circuit. The emitters of the transistors Tr
11
and Tr
12
are connected to a common power supply
3
.
When the input voltage IN4 is greater than the input voltage IN3, the collector current of the transistor Tr
12
decreases. Thus, the base current of an NPN transistor Tr
15
decreases, and the collector current of the transistor Tr
15
decreases. When the collector current of the transistor Tr
15
decreases, the base current of the NPN source output transistor Tr
16
increases, and the collector current of the output transistor Tr
16
increases.
Further, when the collector current of the transistor Tr
15
decreases, the base current of a PNP transistor Tr
17
decreases, and the collector current of the transistor Tr
17
decreases. When the collector current of the transistor Tr
17
decreases, the base current of an output transistor Tr
18
decreases, and the collector current of the output transistor Tr
18
decreases.
When the input voltage IN4 is less than the input voltage IN3, the collector current of the transistor Tr
12
increases. Thus, the base current of the transistor Tr
15
increases, and the collector current of the transistor Tr
15
increases. When the collector current of the transistors Tr
15
increases, the base current of the output transistor Tr
16
decreases, and the collector current of the output transistor Tr
16
decreases.
Further, when the collector current of the transistor Tr
15
increases, the base current of a PNP transistor Tr
17
increases, and the collector current of the transistor Tr
17
increases. When the collector current of the transistor Tr
17
increases, the base current of the NPN sink output transistor Tr
18
increases, and the collector current of the output transistor Tr
18
increases.
The collector current of the transistor Tr
17
is supplied as the collector current of the NPN transistor Tr
19
. An idling current setting circuit, which includes transistors Tr
20
to Tr
22
and a resistor R, control the base current of the transistor Tr
19
.
The idling current setting circuit detects the output voltage Vout and increases the base current of the transistor Tr
19
when the output voltage Vout increases to increase the collector current of the transistor Tr
19
. When the output voltage Vout decreases, the idling current sett

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