Operational amplifier

Details Operational amplifier Operational amplifier

1998-12-07

2001-07-31

Shingleton, Michael B (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S255000, C330S263000

Reexamination Certificate

active

06268769

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly, to an operational amplifier suited for use in portable communication equipment and the like.
2. Description of the Related Art
Japanese Unexamined Patent Publication No. 7-46059 shows a conventional operational amplifier (see FIG.
3
). Referring to
FIG. 3
, an operational amplifier
100
comprises a differential amplifier stage
1
, a current mirror stage
2
, and a buffer circuit
3
. The differential amplifier stage
1
includes first and second differential amplifier circuits
1
a
,
1
b
, respectively, arranged symmetrically with respect to a transverse center line of the circuit. The current mirror stage
2
comprises first and second current mirror circuits
2
a
,
2
b
, respectively, arranged symmetrically with respect to a transverse center line of the circuit. The buffer circuit
3
is connected to the common output of the current mirror circuits
2
a
,
2
b.
The first differential amplifier circuit
1
a
is formed of a pair of NPN transistors Q
1
, Q
2
. The second differential amplifier circuit
1
b
is formed of a pair of PNP transistors Q
3
, Q
4
. The first current mirror circuit
2
a
comprises three PNP transistors Q
5
, Q
6
, and Q
7
. The second current mirror circuit
2
b
is made up of three NPN transistors Q
8
, Q
9
, and Q
10
. The buffer circuit
3
has a diamond arrangement, and includes two NPN transistors Q
11
, Q
13
, and two PNP transistors Q
12
, Q
14
. The buffer circuit is also provided with a PNP transistor Q
15
and an NPN transistor Q
16
which act as current sources. Transistors Q
11
, Q
12
are first and second input transistors, respectively, and transistors Q
13
, Q
14
are first and second output transistors, respectively.
In the above arrangement, the bases of transistors Q
1
, Q
3
(which are taken from the first and second differential amplifier circuits
1
a
,
1
b
, respectively) are connected to a positive-phase input terminal IN
1
. The bases of the remaining transistors Q
2
, Q
4
, are connected to a negative-phase input terminal IN
2
. The collector of transistor Q
1
is the output of the first differential amplifier circuit
1
a
, and is connected to the input of the first current mirror circuit
2
a
. The collector of transistor Q
2
is connected to a positive power source +Vcc. The emitters of transistors Q
1
, Q
2
are directly tied together and are connected to a first constant current circuit
4
a
. Further, the collector of transistor Q
3
is the output of the second differential amplifier circuit
1
b
, and is connected to the input of the second current mirror circuit
2
b
. The collector of transistor Q
4
is connected to a negative power source −Vcc. The emitters of transistors Q
3
, Q
4
are directly tied together and are connected to a second constant current circuit
4
b
. The collectors of transistors Q
7
, Q
10
(which are the outputs of the first and second current mirror circuits
2
a
,
2
b
, respectively) are connected to the positive and negative power sources +Vcc, −Vcc, respectively through respective phase compensating capacitors C
1
, C
2
. In addition, the collectors of transistors Q
7
and Q
10
are directly tied together and connected to the input of the buffer circuit
3
.
In the buffer circuit
3
, transistors Q
15
, Q
16
are used as current sources for transistors Q
11
, Q
12
, respectively. More particularly, the collector of transistor Q
15
is connected to a node between the emitter of transistor Q
12
and the base of transistor Q
13
. The emitter of transistor Q
15
is connected to the positive voltage +Vcc, and the base of transistor Q
15
is connected to the bases of transistors Q
5
, Q
6
(which are directly tied together) in the second current mirror circuit
2
a
. The collector of transistor Q
16
is connected to a node between the emitter of transistor Q
11
and the base of transistor Q
14
. The emitter of transistor Q
16
is connected to the negative voltage −Vcc, and the base of transistor Q
16
is connected to the bases of transistors Q
8
, Q
9
(which are directly tied together) in the current mirror circuit
2
b
. Thus, the buffer circuit
3
is controlled with the operating current flowing in the current mirror stage
2
, depending on an input signal voltage.
For the operational amplifier
100
described above to operate at a high speed and over a wide bandwidth, it is necessary to increase the mutual conductance of the differential amplifier stage
1
(i.e., converting a voltage in a current). To increase the mutual conductance of the differential amplifier stage
1
, one must increase a current flowing in the differential amplifier stage
1
.
In the above-described arrangement of the conventional operational amplifier
100
, the increase of current flowing in the differential amplifier stage
1
is accomplished by enhancing the increasing change-ratio of current flowing in the first current mirror circuit
2
a
of the current mirror stage
2
, and enhancing the decreasing change-ratio of current flowing in the second current mirror circuit
2
b
. As a result, the increasing change-ratio of the current in the first current mirror circuit
2
a
cannot be processed in the buffer circuit
3
. The current which cannot be processed in the buffer circuit
3
begins to flow into the second current mirror circuit
2
b
in which the current is reduced. Accordingly, the second current mirror circuit
2
b
becomes saturated and cannot normally operate.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to solve the above-described problems and to provide an operational amplifier in which a buffer circuit has a reduced input impedance and is capable of processing an increased amount of current.
According to the present invention, there is provided an operational amplifier which includes a differential amplifier stage having a positive input terminal and a negative input terminal, formed of a pair of differential amplifier circuits, a current mirror stage formed of a pair of current mirror circuits and connected to the outputs of the differential amplifier stage, and a buffer circuit having current sources connected to the common output of the current mirror stage, wherein the buffer circuit includes a plurality of first input transistors connected in parallel and a plurality of second input transistors connected in parallel.
Preferably, the buffer circuit further includes a first output transistor and a second output transistor, and has a diamond arrangement formed of the first output transistor, the second output transistor, at least one of the plurality of first input transistors, and at least one of the plurality of second input transistors.
More preferably, the remainder of the plurality of first input transistors and the remainder of the plurality of second input transistors are directly tied together and connected to the output.
In the operational amplifier of the present invention, since the buffer circuit includes the plurality of first input transistors and the plurality of second input transistors, the respective impedances of the plurality of first input transistors and the plurality of second input transistors are in parallel with each other. Thus, the input impedance of the buffer circuit is reduced.


REFERENCES:
patent: 4972158 (1990-11-01), Sutterlin
patent: 5515005 (1996-05-01), Yoshioka

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