Operation timing controllable system

Details Operation timing controllable system Operation timing controllable system

1999-04-14

2001-02-27

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S291000, C327S295000

Reexamination Certificate

active

06194926

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a system including a plurality of circuit blocks, and more particularly relates to a technique of controlling operation timing in such a manner as to suppress coincident switching noise.
In recent years, a semiconductor integrated circuit is composed of a plurality of circuit blocks in many cases. For example, a microcontroller unit (MCU) is made up of CPU, memory and other circuit blocks of numerous types.
Under the circumstances such as these, noise is more likely to be caused these days in a semiconductor integrated circuit mainly because of charging and discharging of gate and line capacitances formed by the increased number of circuit blocks included. If these circuit blocks charge and discharge simultaneously, then large noise is caused within the overall system. Such noise is generally called “coincident switching noise”.
In a prior art technique for suppressing the coincident switching noise in a system including a plurality of circuit blocks, a delay circuit is provided for delaying a reference clock signal externally supplied. In this configuration, each circuit block is selectively supplied with the reference clock signal or a delayed clock signal responsive to a switching signal. This technique is disclosed in Japanese Laid-Open Publication No. 10-91274, for example.
In some of real-world circuits, a peak current state arises immediately after a clock signal has risen. In other circuits, however, the occurrence of the peak current state is delayed for some time after a clock signal has risen. For instance, if a large-scale combinatorial circuit, included in a circuit block, starts to operate later than a clock signal supplied to the circuit block, then the occurrence of a peak current state in this circuit block is delayed for a while after the clock signal has risen. Also, the delay time is variable with the internal configuration of a specific circuit block.
The prior art identified above supposes that a peak current state always arises soon after a clock signal has risen, and pays no attention to the possibilities that the peak current state may at different times in respective circuit blocks. Accordingly, in accordance with this technique, if a circuit block, where a peak current state arises later than the leading edge of a clock signal, is included in a system, then the coincident switching noise cannot always be suppressed.
SUMMARY OF THE INVENTION
An object of the present invention is ensuring the suppression of coincident switching noise for a system including a plurality of circuit blocks no matter when the peak current state arises in these circuit blocks.
Specifically, an operation timing controllable system according to the present invention includes: a plurality of circuit blocks; and means for controlling operation timing of the circuit blocks by supplying associated operation control signals thereto. The operation timing control means memorizes respective times when a peak current state occurs in the individual circuit blocks responsive to the associated operation control signals, and controls the timing of the operation control signals in accordance with the memorized times when the peak current state occurs.
According to the present invention, the times when the peak current state arises in the individual circuit blocks responsive to the associated operation control signals are memorized at the operation timing control means. And the timing of the operation control signals is controlled in accordance with the memorized times when the peak current state arises. Thus, even it the peak current state arises at respectively different times in the individual circuit blocks, the coincident switching noise can be suppressed with a lot more certainty.
In one embodiment of the present invention, the control means preferably controls the timing of the operation control signals such that the peak current state arises at discrete time in the respective circuit blocks.
In another embodiment, the control means preferably includes: a signal generator for generating a plurality of timing signals at respectively different times in response to a reference clock signal; and a signal selector for selecting any of the timing signals, generated by the signal generator, as associated one of the operation control signals to be supplied to each said circuit block.
Another operation timing controllable system according to the present invention includes: a plurality of circuit blocks; and means for controlling operation timing of the circuit blocks by supplying associated operation control signals thereto. Each said circuit block includes a peak current detector for detecting a time when a peak current state arises in the circuit block responsive to associated one of the operation control signals supplied thereto. The operation timing control means controls the timing of the operation control signals in accordance with the times, at which the peak current state arises in the respective circuit blocks and which have been detected by the peak current detectors.
According to the present invention, a peak current detector, provided for each circuit block, detects a time when the peak current state arises in the circuit block responsive to associated one of the operation control signals supplied thereto. And the timing of the operation control signals is controlled in accordance with the times when the peak current state arises in the respective circuit blocks. Thus, even if the peak current state arises at respectively different times in the individual circuit blocks, the coincident switching noise can be suppressed with a lot more certainty.
In one embodiment of the present invention, the peak current detector preferably includes: a resistor inserted in a current supply path between a power supply and the circuit block associated with the detector; and a comparator with an offset voltage for receiving a voltage difference between both terminals of the resistor as a differential input.
In another embodiment, the control means preferably controls the timing of the operation control signals such that the peak current state arises at discrete times among the circuit blocks.
In still another embodiment, the control means preferably includes: a signal generator for generating a plurality of timing signals at respectively different times in response to a reference clock signal; and a signal selector for selecting any of the timing signals, generated by the signal generator, as associated one of the operation control signals to be supplied to each said circuit block.


REFERENCES:
patent: 4644195 (1987-02-01), Miller et al.
patent: 4686480 (1987-08-01), Katto et al.
patent: 4-302014 (1992-10-01), None
patent: 9-34580 (1996-06-01), None
patent: 10-91274 (1998-04-01), None

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