Operation mode setting circuit for dram

Details Operation mode setting circuit for dram Operation mode setting circuit for dram

1989-02-08

1991-01-08

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365222, 36518905, G11C 800

Patent

active

049842161

ABSTRACT:
A signal externally supplied to determine the operation mode is supplied to a first buffer circuit. A CAS signal is supplied to a second buffer circuit. The signals whose levels are converted by the first and second buffer circuits are supplied to a mode selection circuit. The operation of the mode selection circuit is controlled by a RAS signal, and it latches and outputs a mode selection signal based on the outputs of the first and second buffer circuits. An externally supplied address signal and an address signal formed in the device are supplied to address buffer circuit. The address buffer circuit selects one of the received address signals based on the RAS signal anad the mode selection signal output from the mode selection circuit. A selected one of the address signals is supplied to a word line selection/driving circuit. When a mode other than the auto-refresh mode is specified, the mode setting signal is set up before the RAS signal is activated. The set-up allowance time with respect to the activation timing of the RAS signal is set to be larger than the minimum value of the set-up allowance time of the external address signal. The mode setting signal is latched by the mode selection circuit when the RAS signal is activated. The latched signal is used to select and control the operation mode.

REFERENCES:
patent: 4802135 (1989-01-01), Shinoda et al.
Nikkei Electronics, 1987, 10.5 (No. 431), pp. 115-130 at p. 125.

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