Operation methods for a non-volatile memory cell in an array

Details Operation methods for a non-volatile memory cell in an array Operation methods for a non-volatile memory cell in an array

2007-09-18

2007-09-18

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185250

Reexamination Certificate

active

11020269

ABSTRACT:
A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.

REFERENCES:
patent: 6411548 (2002-06-01), Sakui et al.
patent: 6616070 (2003-09-01), Kunkulagunta
patent: 6825084 (2004-11-01), Ogura et al.
patent: 6894924 (2005-05-01), Choi et al.
patent: 2004/0145024 (2004-07-01), Chen et al.
patent: 2006/0049448 (2006-03-01), Yeh

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