Operation control apparatus for a processor having a plurality o

Details Operation control apparatus for a processor having a plurality o Operation control apparatus for a processor having a plurality o

1988-04-08

1990-10-30

Fleming, Michael R.

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364900, 364258, 364263, 3642318, 3649371, 3649235, 36494834, 3649462, G06F 938, G06F 930, G06F 1200, G06F 700

Patent

active

049673394

ABSTRACT:
A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a way that a high order 32 bit operation is performed in an arithmetic device in the operand effective address unit and a low order 32 bit operation is performed in another arithmetic device in the instruction execution unit. A carry is transferred from the low order 32 bit arithmetic device to the high order 32 bit arithmetic device. The arithmetic devices thus joined can perform the 64 bit with data operation as an arithmetic device.

REFERENCES:
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patent: 4434459 (1984-02-01), Holland et al.
patent: 4594655 (1986-06-01), Hao et al.
patent: 4616313 (1986-10-01), Aoyagi
patent: 4626989 (1986-12-01), Torii
patent: 4698747 (1987-10-01), Thompson et al.
patent: 4766566 (1988-08-01), Chuang

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