Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-10-05
2003-05-27
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S253000
Reexamination Certificate
active
06570449
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an operation amplification circuit that is capable of low current consumption, is not dependent on the power supply voltage, and can reduce variations in the mass production to the minimum level, and a constant voltage circuit that uses the operation amplification circuit.
2. Description of Related Art
A conventional operation amplification circuit is shown in FIG.
11
. The operation amplification circuit is equipped at least with a bias circuit
1
, a differential amplification circuit
2
, and an output amplification circuit
3
, as shown in FIG.
11
.
The bias circuit
1
is a circuit that generates a reference voltage and makes constant a current flowing in a NMOS transistor Q
7
of the differential amplification circuit
2
and a current flowing in a NMOS transistor Q
9
of the differential amplification circuit
3
. For this reason, as shown in
FIG. 11
, the bias circuit
1
has a PMOS transistor Q
1
and an NMOS transistor Q
2
serially connected to one another, and the serial circuit is connected between power supply lines
4
and
5
.
The differential amplification circuit
2
is a circuit that differentially amplifies a differential signal, and as shown in
FIG. 11
, is formed from a differential pair of NMOS transistors Q
3
and Q
4
that is biased by an NMOS transistor Q
7
that provides a constant current source. The NMOS transistors Q
3
and Q
4
are connected to a current mirror circuit that is formed from PMOS transistors Q
5
and Q
6
as an active load.
The output amplification circuit
3
amplifies and outputs an output signal of the differential amplification circuit
2
by a PMOS transistor Q
8
with an NMOS transistor Q
9
that is an active load.
In the bias circuit
1
of the conventional operation amplification circuit with the structure described above, the PMOS transistor Q
1
can be operated in both of the linear region and the saturation region. Current I that flows in the PMOS transistor Q
1
is considered below in both of the cases in which the PMOS transistor Q
1
is operated in the linear region and the saturation region.
First, when the PMOS transistor Q
1
operates in the linear region, and the power supply voltage VSS is zero (VSS=0), the current I that flows in the PMOS transistor Q
1
is provided by Formula (1) as follows:
I
=
β
0
×
(
W
/
L
)
{
(
V
GS
-
V
TP
)
×
V
DS
-
1
/
2
×
(
V
DS
)
2
}
=
β
0
×
(
W
/
L
)
{
(
VDD
-
V
TP
)
×
(
VDD
-
V1
)
-
1
/
2
×
(
VDD
-
V1
)
2
}
(
1
)
Also, when the PMOS transistor Q
1
operates in the saturation region, the current I that flows in the PMOS transistor Q
1
is provided by Formula (1A) as follows:
I
=
1
/
2
×
β
0
×
(
W
/
L
)
(
V
GS
-
V
TP
)
2
=
1
/
2
×
β
0
×
(
W
/
L
)
(
VDD
-
V
TP
)
2
(1A)
The determination as to which of the regions that the PMOS transistor Q
1
operates is made depending on which of the threshold voltages, the threshold voltage V
TP
of the PMOS transistor Q
1
or the threshold voltage V
TN
of the NMOS transistor Q
2
, is larger or smaller than the other. When V
TP
>V
TN
, the PMOS transistor Q
1
operates in the saturation region.
In the above Formulas, &bgr;
0
is a constant determined by the process, W is a channel width of the PMOS transistor Q
1
, L is a channel length of the same, VDD is a power supply voltage, V
1
is a drain voltage of the NMOS transistor Q
2
, and V
TP
is a threshold voltage of the PMOS transistor Q
1
.
Also, the PMOS transistor is an enhancement type transistor when it has a positive threshold voltage, and is a depletion type transistor when it has a negative threshold voltage. The description is made throughout the present specification according to this definition.
As indicated in the above Formula (1) and Formula (1A), the current I that flows in the PMOS transistor Q
1
depends on the power supply voltage VDD in either the linear region or the saturation region, and increases generally in proportion to the square of the power supply voltage VDD. Also, the current I determines bias currents that flow in the MOS transistors Q
2
, Q
7
and Q
9
. Accordingly, since the bias current increases in proportion to the square of the power supply voltage VDD, a problem occurs in that the overall power consumption of the operation amplification circuit increases when the power supply voltage VDD varies (increases).
On the other hand, the threshold voltage V
TP
of the PMOS transistor Q
1
is generally determined by Formula (2) as follows.
V
TP
=−{2&phgr;
F
+&phgr;
M
−&phgr;
S
−(
Q
B
/C
0
)−(
Q
SS
/C
0
)} (2)
In Formula (2), &phgr;
F
is Fermi level of the silicon substrate, &phgr;
M
is a work function of the gate electrode, &phgr;
S
is a work function of the silicon substrate, Q
B
is a charge amount in the surface of the silicon, Q
SS
is an interfacial charge amount between the silicon and the oxide film, and C
0
is a capacity per unit area of the gate.
Accordingly, since the threshold voltage V
TP
of the PMOS transistor Q
1
is dependent on six parameters, as indicated in Formula (2), variations in the threshold voltage V
TP
become large. As a result, a problem occurs in that variations in the manufacturing process also cause variations in the current consumption.
SUMMARY OF THE INVENTION
Accordingly, it is a first object of the present invention to provide an operation amplification circuit that is capable of reducing the current consumption, is not dependent on the power supply voltage, and can reduce variations in the mass production to a minimum.
Also, it is a second object of the present invention to provide a constant voltage circuit that uses the above operation amplification circuit, which is capable of reducing the current consumption, is not dependent on the power supply voltage, and can reduce variations in the mass production to a minimum.
Furthermore, it is a third object of the present invention to provide a reference voltage circuit that can generate a reference voltage that is not dependent on the power supply voltage.
The invention achieves the first object of the invention as discussed below.
Namely, the present invention in accordance with a first aspect includes a differential amplification circuit that receives a differential signal and performs a differential amplification thereof, an output amplification circuit that amplifies an output of the differential amplification circuit, and a bias circuit that determines a bias of the differential amplification circuit and the output amplification circuit. The bias circuit includes a reference voltage circuit that generates a specified reference voltage, and a current mirror circuit based on the reference voltage generated by the reference voltage circuit. The reference voltage circuit includes a first MOS transistor and a second MOS transistor of an identical conduction type that are serially connected to one another. A gate electrode of the first MOS transistor is formed from polysilicon including a P-type impurity and connected to a source electrode thereof, and a gate electrode of the second MOS transistor is formed from polysilicon including an N-type impurity and is connected to a drain electrode thereof. A voltage corresponding to a difference between threshold voltages of the MOS transistors is generated at a common connection section of the MOS transistors as the reference voltage.
In the operation amplification circuit discussed above, the first MOS transistor can be a depletion type transistor and the second MOS transistor can be an enhancement type transistor.
In the operation amplification circuit discussed above, the first MOS transistors can be serially connected in a plurality of stages.
By the inventions set forth above, the reference voltage circuit can generate a reference voltage that is not dependent on the power supply voltage, whereby a bias current (current consu
Oliff & Berridg,e PLC
Seiko Epson Corporation
Shingleton Michael B
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