Operating voltage selection circuit for non-volatile semiconduct

Static information storage and retrieval – Floating gate – Particular biasing

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365233, 365226, 36518518, G11C 1606

Patent

active

061011274

ABSTRACT:
An operating voltage selection circuit for non-volatile semiconductor memories, comprising: means (1) for reading at least one one-time programmable non-volatile memory cell (10), suitable to generate a signal (LV) which indicates the requested type of operating voltage of a non-volatile memory, which depends on the programmed or non-programmed state of the memory cell; memory enabling means (5), which comprise an inverter (30, 31) and are provided with means (32) for modifying the switching threshold of the inverter as a function of the signal that indicates the requested type of operating voltage; output means (2), which are connected to means for sensing data of the memory and to output terminals of the memory, comprising a CMOS inverter (20, 50) and means (23) for modifying the output current of the inverter as a function of the signal (LV) for indicating the requested type of operating voltage; and means (8) for the internal synchronization of the memory, which comprise pluralities of transistors (40, 41, 42) connected in a series/parallel configuration which is determined by the signal (LV) for indicating the requested type of operating voltage, in order to generate signals (CK1, CK2, CK3) for the internal synchronization of the memory.

REFERENCES:
patent: 5363335 (1994-11-01), Jungroth et al.
patent: 5615151 (1997-03-01), Furuno et al.
patent: 5889719 (1999-03-01), Yoo et al.
patent: 5912856 (1999-06-01), Lee et al.
patent: 5930170 (1999-03-01), Kunst et al.
EPO, Partial European Search Report, Jul. 21, 1998, EP 98830104.

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