Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1997-01-27
2001-04-03
Maung, Zarni (Department: 2151)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
Reexamination Certificate
active
06212576
ABSTRACT:
APPENDIX
Attached hereto is an Appendix which is written in the C program language containing pages A1 and A2 which is an example of the operating system interface mapping layer
124
of
FIG. 3
in accordance with the present invention. The code of the Appendix maps the universal and generic instruction set used for programming tasks of the multilayer protocol stack
122
onto the instruction set of the CMX operating system for execution on a Siemens 8016C microprocessor. Specifically, the routines contained in the Appendix map the GSMSendMessage, GSMGetMessage, GSMDisableInterrupts and GSMRestoreCPUState instructions of the multilayer protocol stack onto the instruction set of the CMX operating system so that the multilayer protocol stack is independent of the underlying operating system. The subject matter of the Appendix is copyrighted and a limited license is granted for the purpose of copying the program disclosed therein for purposes of understanding or analyzing the invention but no rights are granted to make a copy for any other purpose including the loading of a processing device with the code of the Appendix in any form or language.
TECHNICAL FIELD
The present invention relates to GSM transceiving units and more particularly to portable multilayer protocol stacks for use in GSM transceivers in which the portable multilayer protocol stack is adaptable to different operating systems without rewriting thereof.
BACKGROUND ART
The GSM communication system (global system for mobile communications) is a TDMA telecommunications system providing time multiplexed communications between mobile units and base stations contained in the GSM communication system. The GSM communication system, including transceiver units, is defined by published specifications which have been adopted over the years.
The functionality of a GSM transceiver in the GSM communication system is defined by the aforementioned GSM specifications and includes a multilayer protocol stack containing software executed with a microprocessor. A first layer of the protocol stack interfaces with the hardware and controls communications to and from the second and third protocol layers. The second and third protocol layers control communications to and from the first layer and utilize services provided by the first protocol layer to communicate with the GSM network. The communications between the GSM network and GSM transceivers are time multiplexed into GSM frames. Each GSM frame has a fixed time duration and is divided into multiple segments each containing a plurality of bits all in accordance with the aforementioned published GSM specifications.
FIG. 1
illustrates a block diagram of a prior art transceiving unit which is disclosed in a catalog entitled “ICs for Communications” published by Siemens AG and identified as Product Overview 09.95. Standard functional notations are utilized to identify the functional elements in the block diagram of FIG.
1
. Only a brief overview description of
FIG. 1
will be given to describe the overall design of a GSM transceiver in which the present invention may be practiced and its relationship to a GSM network.
The GSM transceiver
10
is a double conversion heterodyne PM receiver with phase shifting circuitry for I/Q demodulation. Antenna
12
is connected through filter
14
to low noise amplifier
16
which is in turn connected to filter
18
. The output of filter
18
is connected to mixer
20
which shifts the received signal down to an intermediate frequency. The output of mixer
20
is connected to filter
22
and the output of filter
22
is connected to amplifier
24
. The output of amplifier
24
is connected to mixer
26
which shifts the signal to the baseband. The output of mixer
26
is connected to amplifiers
28
whose I and Q outputs are respectively connected to filters
30
having outputs applied to A to D converters
32
. The outputs of the A to D converters
32
are connected to a digital signal processor
34
which includes filters
36
which are connected to the outputs of the A to D converters
32
, a soft equalizer
38
which is connected to the output of the filters
36
and a speech and channel decoder
40
. The output of the speech and channel decoder
40
is connected to filter
42
whose output is connected to D to A converter
44
whose output is applied to amplifier
46
which drives speaker
48
to provide audio to a user. Speech of the user is detected by microphone
50
which is connected to amplifier
52
having an output connected to A to D converter
54
. The output of A to D converter
54
is connected to filter
56
having an output connected to speech and channel encoder
58
. The outputs of speech and channel encoder
58
are connected to a GMSK encoder
60
having a pair of outputs which are applied to D to A converters
62
with the outputs thereof being connected to filters
64
which respectively output I and Q signals. The I and Q signals are connected to mixers
66
which are driven by RFVCO
68
to convert the signal from the baseband to the RF band. The output of mixers
66
is connected to output stage
68
′. The output of output stage
68
′ is connected to filter
70
. The output of filter
70
is connected to output amplifier
72
which is controlled by a power amplifier control
74
in the form of a D to A converter. Microprocessor
76
controls the overall system including the power amplifier control
74
and provides a system interface
77
. The system interface
77
generates chip select signals, internal clock signals, GSM specific control and timing signals via programmable timers for programmable interrupts on timer values and provides a chip card interface to a SIM card
78
. The interface
77
also provides connectivity to a keypad
80
. The microprocessor
76
is connected to a E
2
PROM
82
, a flash memory
85
, and RAM
86
.
As illustrated, a GSM network
84
, which is in accordance with GSM specifications including base stations and related switching architecture, transmits and receives communications between individual transceiver units
10
via RF transmission
87
. The communications are time multiplexed into GSM frames each containing
8
time slots each containing multiple bits. Base stations (not illustrated) of the GSM network
84
each have an antenna
88
which transmits and receives the aforementioned time multiplexed GSM frames.
Each GSM transceiver, such as the unit
10
illustrated in
FIG. 1
in accordance with the published GSM specifications, has a multilayer protocol stack including first, second and third layers. Instructions must be issued to the hardware to allow the hardware to perform in accordance with the published GSM specifications in the GSM frames with either a frame advance or a frame delay which is required to be an integer multiple of the time duration of a GSM frame. This permits designers of hardware for implementing GSM transceivers to provide for pipeline frame delays or frame advances in terms of an integer multiple of the time duration of a GSM frame between the protocol stack and the hardware which suit the design requirements of the hardware. The first three layers of the GSM protocol stack conforms to the overall OSI network model for providing a universal multi-layer protocol stack.
In order to provide the functionality of the first three layers of the multilayer protocol stack of the GSM specifications, substantial software is required. This software requires substantial time and effort to write and is complex. Furthermore, because of the diversity of the designs used by the numerous manufacturers of chipsets used in GSM transceivers and operating systems, the software required to implement the first three layers of the protocol stack of a GSM transceiver is uniquely suited to and developed for a particular chipset which prevents the protocol stack from being portable to other chipiets and operating systems and therefore usable with other chipsets and operating systems without substantial rewriting of the code contained therein. A need exists in the art for
Dickstein , Shapiro, Morin & Oshinsky, LLP
Fourson Gary S.
Maung Zarni
Optimay Corporation
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