Operating clock generation system and method for audio...

Details Operating clock generation system and method for audio... Operating clock generation system and method for audio...

2008-12-08

2010-06-08

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S156000

Reexamination Certificate

active

07733151

ABSTRACT:
A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).

REFERENCES:
patent: 7200093 (2007-04-01), Hsiao et al.
patent: 7262716 (2007-08-01), Yu et al.
patent: 7408485 (2008-08-01), Yu et al.
patent: 7432750 (2008-10-01), Sidiropoulos et al.
patent: 2005/0017772 (2005-01-01), Hsiao et al.
patent: 2005/0093593 (2005-05-01), Fukuzawa et al.
patent: 2008/0111597 (2008-05-01), Cranford et al.

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