Operating circuit and method for processing signals in ADPCM sys

Details Operating circuit and method for processing signals in ADPCM sys Operating circuit and method for processing signals in ADPCM sys

1995-12-20

1998-06-09

Pan, Daniel H.

Boots, shoes, and leggings

395387, 364DIG1, 364DIG2, G06F 932, G06F 9355

Patent

active

057649413

ABSTRACT:
An operating circuit carrying out a conditional branch to judge a value level of a calculated result output from an arithmetic logic unit (ALU) during one machine cycle, using an address unit, realizes shorter processing time and low power consumption. The operating circuit sequentially carries out calculations according to command codes in a command ROM and includes a result register for storing and outputting the calculated result of the ALU; a value level judgement mechanism for judging a value level of an output of the result register; a latch for storing a current value of a program counter; an adder for calculating a next value of a program counter by adding a value level judgement result from the value level judgement mechanism and a current value of the program counter stored in the latch; and a first selector for selecting an added result and for deciding a next command address in the command ROM, a conditional branch being carried out to a command address corresponding to a value level obtained for the calculated result from the ALU.

REFERENCES:
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patent: 5161247 (1992-11-01), Murakami
patent: 5410660 (1995-04-01), Divine et al.
patent: 5450555 (1995-09-01), Brown, III et al.
"ADPCM Encoder/Decoder"; International Telecommunication Union Recommendation G.726; 1990.
Bodner, et al. "Accelerated Instruction Execution of BC/JC Instructions." IBM.RTM. Technical Disclosure Bulletin vol. 19, No. 3 Aug., 1976 (pp. 1051-1053).

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