Operating a non-volatile memory device

Details Operating a non-volatile memory device Operating a non-volatile memory device

2005-05-17

2005-05-17

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

C365S185170, C365S185180, C365S185290

Reexamination Certificate

active

06894924

ABSTRACT:
An operation method of programming, erasing, and reading a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device having a tunnel oxide layer thicker than 20 Å is provided. A program operation of the method is accomplished by applying a program voltage higher than 0 volts and a ground voltage to a gate electrode and a channel region of a selected SONOS cell transistor, respectively. Also, an erasing operation is accomplished by applying a ground voltage and a first erase voltage lower than 0 volts to a bulk region and a gate electrode of a selected SONOS cell transistor, respectively, and by applying a second erasure voltage to either a drain region or a source region of the selected SONOS cell transistor. The second erase voltage is a ground voltage or a positive voltage. In addition, a read operation is accomplished using either a backward read mode or a forward read mode. Thus, it is possible to remarkably improve a bake retention characteristic, which is sensitive to a thickness of the tunnel oxide layer.

REFERENCES:
patent: 6122191 (2000-09-01), Hirose et al.
patent: 6597604 (2003-07-01), Yi et al.
patent: 10-065029 (1998-03-01), None
patent: 11-126494 (1999-11-01), None
English language Abstract from Japanese Patent Publication No. 10-065029.
English language Abstract from Japanese Patent Publication No. 11-126494.

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