Open loop supply independent digital/logic delay circuit

Details Open loop supply independent digital/logic delay circuit Open loop supply independent digital/logic delay circuit

1999-10-08

2001-07-17

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S285000, C327S288000, C327S538000, C327S537000, C331S057000

Reexamination Certificate

active

06262616

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of timing integrated circuits and, more particularly, to circuits for providing timing delays.
2. Background of the Related Art
The use of delay circuits to delay a signal has many applications in circuit design. Generally, a delay circuit operates by receiving an input signal and generating an output signal which is delayed by some time period from the input signal. The output can be a reproduction of the input signal delayed by some time t or it can be a separate signal commencing at the delayed time t from the input signal. For example, the input signal can be a digital clocking signal and the output signal can be a delayed clocking signal, so that a positive edge transition of the output clock signal is delayed by time t from the positive edge transition of the input signal.
In some instances, it is desirable to output more than one clocking signal based on a reference input. For example, for a given reference input, a first delayed signal is generated at time t
1
and a second delayed signal is generated at time t
2
. The triggering of the second delayed signal can be based on the reference signal or the first delayed signal. For example, after the first signal commences at delay time t
1
, it can be made to transition again (return to the original state) at time t
2
. This second transition of the first signal can be used to trigger the second output signal. Clocking schemes of this type are utilized when two delayed clocking signals are required, but where the second signal is to occur after completion of the first.
A problem with this type of scheme is that the second output is dependent on the first for the timing. Any variations in the delay of the first output will impact the commencement of the second output. In a circuit where the first output triggers the second output, delay variations of the first output will alter the delay of the second output. It may further alter the pulse-width of the second output, in the instance the second clocking signal is made to transition again (return to the original state) at the transition of the original reference signal.
Accordingly, maintaining a relatively steady delay for the output signals, especially for the first signal, allows for tighter design tolerances. In order to achieve better control of delays, closed loop controls can be used. For example, a delay lock loop (DLL) can be used to adjust for any delay variations. DLLs are effective, but require more circuit complexity to provide the feedback to correct for unwanted variations in the signal. Alternatively, open loop control mechanisms can be used. Open loop systems are simpler to implement than closed loop systems, but may be more susceptible to circuit and environment variations, such as changes in temperature, supply voltage or process parameters which affect transistor performance (process corners). Where these variations are encountered, the open loop system may have difficulty in maintaining the desired delay in the delay circuit described above.
The present invention addresses the above concern of providing a desired delay, while utilizing an open loop control system to maintain the delay substantially steady with respect to supply voltage.
SUMMARY OF THE INVENTION
An open-loop supply independent digital/logic delay circuit is described. A delay circuit, comprised of a series of inverters, receives an input reference signal and generates an output which is delayed from the input signal. The delay is achieved by the response of each stage in transitioning the input signal to the next stage. A bias circuit is coupled to the delay circuit and utilized to control the current flow in the inverter stages, so that when a voltage to the inverter changes, the current flow is changed substantially proportionally to the voltage to maintain the delay substantially constant with respect to the voltage.


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