Open loop digital frequency multiplier

Details Open loop digital frequency multiplier Open loop digital frequency multiplier

1975-11-10

1977-05-24

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307225R, 328 39, 328 48, 328 63, H03K 500, H03K 2132

Patent

active

040258661

ABSTRACT:
An open loop digital frequency multiplier with a multiplied output synchonized to low frequency clock pulses. The system includes a multi-stage digital counter which provides a pulse output as a function of an integer divisor. The integer divisor and the timing or counting cycle of the counter are interrelated to the frequency of a clock input. The counting cycle is controlled by a one-shot multivibrator which, in turn, is driven by a reference frequency input.

REFERENCES:
patent: 3579126 (1971-05-01), Paul
patent: 3657658 (1972-04-01), Kubo
patent: 3673391 (1972-06-01), Lougheed
patent: 3716794 (1973-02-01), Teggatz et al.
patent: 3835396 (1974-09-01), Demos et al.
"A New Type of Digital Frequency Multiplier," by Horelick et al., Proceedings of the IEEE, Sept. 1975, [pp. 1365-1366].

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