Open input sense for differential receiver

Details Open input sense for differential receiver Open input sense for differential receiver

2003-01-16

2004-02-17

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S075000

Reexamination Certificate

active

06693465

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to differential receivers. More particularly, the present invention relates to sensing when inputs to the differential receiver are not connected to a driving source.
DESCRIPTION OF RELATED ART
Current electronic systems, such as computer processors, data switches, data storage systems, and the like, must send data back and forth from processor to processor, from data storage systems to processor, or in general, from any electronic unit to another electronic unit that must communicate. For example, a processor may require data that resides on a data storage system such as a hard disk. To get the data, the processor typically sends a request for the data over signal interconnections to the storage system. The request typically contains addressing data and perhaps an amount of data to be retrieved. The storage system receives and interprets the request, retrieves the data from its storage medium (e.g., hard disk), and transmits the data back to the processor.
Performance of the electronic system is highly dependent upon the rate of data transmission between one unit and another unit. In the example of the computer system wherein the processor requires data resident in the storage system, in many cases, the processor is idle until the processor receives the data. Many modern computer processors have more than one task assigned to a processor. In such cases, the processor can usually begin or reawaken other tasks while awaiting data from the storage system for the task requiring data from the storage system. Nonetheless, high-speed data transmission is very important in maximizing throughput in the computer system.
Data is typically routed on electrically conducting signal wires in one of two techniques. A first technique, known as single-ended signaling, uses a single wire for a single signal and references the signal to a voltage supply. Return currents typically flow through a voltage supply plane on a printed wiring board (PWB) or through supply conductors in cabling through which the signal wire is passed. The return currents may be passed through capacitors of suitable capacitance values and suitably low resistive and inductive parasitics from one voltage supply to another, if a single voltage supply cannot be continuously routed near the signal wire.
A receiver of a single-ended signal must compare the voltage of the signal against a voltage referenced to one or more supplies at the receiver. For example, if the signal switches from a first voltage (e.g., ground) to a second voltage (e.g., Vdd), the receiver may interpret a signal voltage exceeding (Vdd-ground)/2 as a logical “1”, and a signal voltage less than (Vdd-ground)/2 as a logical “0”. Unfortunately, the local supply voltages at the receiver may not be exactly the same as the supply voltages at the driver of the single-ended signal. Supply voltages may in fact be (and usually are, for electronic units physically separated by significant distance) voltage supplies created by different power supplies. Furthermore, local supply “bounce” voltage aberrations are caused by switching of large numbers of other signals on a semiconductor chip upon which the driver resides or upon which the receiver resides. All these factors result in significant uncertainty in determining exactly when a single-ended signal is actually interpreted as a “1” or a “0”.
A second signaling technique is called differential signaling. The second technique is typically used in very high-speed signaling, especially when significant distances are involved, and uses two electrical conductors per signal. A first phase of the data, referred to as a positive phase, is sent on a first conductor. A second phase of the data, referred to as a negative phase, is sent on a second conductor. The two phases carry the same data, but are complementary. For example, consider a design wherein an uplevel is 2 volts and a downlevel is 1 volt. A logical “1” is on the differential signal when the positive phase is at 2 volts and the negative phase is at 1 volt. When a logical “0” is on the differential signal, the positive phase is at 1 volt and the negative phase is at 2 volts. A driver of the differential signal is advantageously designed to cause transitions of the positive phase and the negative phase to occur at substantially the same time and at substantially the same speed (i.e., dV/dt) on the two conductors.
A differential receiver receiving a differential signal does not have to interpret either phase of the differential signal versus a voltage supply at the receiver. Rather, the differential receiver merely needs to determine whether the positive phase or the negative phase is of higher voltage. Differential receivers typically comprise a differential amplifier having suitable “common mode” range to determine whether the differential signal is “1” or “0”.
“Common Mode” range denotes the voltage range of the inputs through which the differential amplifier operates properly. For example, suppose that a differential driver drives a 1-volt to 2-volt differential signal. Further suppose that there is a −0.5 volt “ground shift” between the driver and the receiver, which is to be expected, especially if the driver and the receiver are many meters apart. The receiver would see the signals at 1.5 volts to 2.5 volts due to the shift. The differential receiver, as explained above, simply compares the positive phase voltage to the negative phase voltage. The differential amplifier in the example, however, has to be able to perform the comparison when both signals are 0.5 volt higher than would nominally be expected.
Differential signals are frequently used to transmit data over significant distances, and pluggable cables are often used for the signaling conductors. Pluggable cables create a problem, in that a particular cable may not be plugged in properly. Furthermore, in a particular electronic system, a particular differential receiver may be deliberately left unconnected to any driven differential signal. For example, a particular electronic system may have an electronic unit capable of receiving 16 differential signals in a fully configured system, but sold with only 8 differential signals actually used in a subset configuration, with the other 8 receivers not coupled to driven differential signals. Differential receivers not coupled to driven differential signals should output a predictable logical value, e.g., a “1” or a “0”. Care must be taken to ensure that a differential receiver that is not coupled to a driven differential signal does not oscillate, which could occur if both of the undriven inputs were at substantially the same voltage. Both of the disconnected inputs of a differential receiver are typically coupled together by a terminator, and would therefore be at substantially the same voltage.
A number of techniques exist to ensure that a differential receiver outputs a known logical value when the differential receiver inputs are not coupled to a differential signal. For example,
FIG. 1
shows differential receiver
100
, having a differential receiver input port comprising inputs INP
107
and INN
108
, and comprising differential amplifier
105
coupled to INP
107
and INN
108
. A terminator comprising R
101
and R
102
is shown. Such a terminator is commonly placed between the inputs of a differential receiver to electrically terminate a differential signaling pair of conductors, often referred to as a transmission line. A high-valued pulldown resistor R
103
is coupled to the midpoint connection between R
101
and R
102
. The other end of R
103
is coupled to a voltage supply −V
109
. Pulldown resistor R
103
pulls both INP
107
and INN
108
to the voltage of −V
109
when INP
107
and INN
108
are disconnected from a driven differential signal. −V
109
, in the example, is less than V
REF
110
. Comparator
104
detects that a first comparator input, coupled to the midpoint connection between R
102
and R
103
is below V
REF
110
and outputs a logical “0”. AND
106

Affiliated with

Also associated with

Rating

Open input sense for differential receiver does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Open input sense for differential receiver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Open input sense for differential receiver will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3327942