Open drain output driver having digital slew rate control

Details Open drain output driver having digital slew rate control Open drain output driver having digital slew rate control

1996-11-15

1998-07-14

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Slope control of leading or trailing edge of rectangular or...

327379, 327108, H03K 512, H03K 1716

Patent

active

057810508

ABSTRACT:
An open drain driver circuit includes first and second NMOS driver transistors, a delay circuit, an OR gate and an AND gate. Each NMOS driver transistor has a drain coupled to an output terminal, a source coupled to a supply terminal, and a gate. The delay circuit has an input coupled to the input terminal and has an output. The OR gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the first NMOS transistor. The AND gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the second NMOS transistor.

REFERENCES:
patent: 4638187 (1987-01-01), Boler et al.
patent: 4825101 (1989-04-01), Walters, Jr.
patent: 4987324 (1991-01-01), Wong et al.
patent: 5111064 (1992-05-01), Ward
patent: 5410262 (1995-04-01), Kang
patent: 5483188 (1996-01-01), Frodsham
patent: 5512854 (1996-04-01), Park

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