Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-03-04
2004-07-27
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S771000, C257S761000, C257S762000
Reexamination Certificate
active
06768203
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the formation of structures which form barrier or liner layers in semiconductor devices. More particularly, this invention relates to the formation of liner structures which create insulation and diffusion barriers at the sidewalls of a via but not the bottom of a via.
BACKGROUND OF THE INVENTION
A semiconductor chip contains an array of devices whose contacts are interconnected by patterns of conductive wires. In order to take full advantage of the device and circuit density on a given chip, it is usually necessary to make interconnections among the various devices and circuit elements in the chip. However, due to the level of integration of devices and circuits on a chip, interconnections can no longer be made by means of a single level network of conductive lines. Often, it is necessary to form two or more such levels of conductive lines which are vertically spaced apart and separated by intermediate insulating layers.
Connections can made between the different levels of conductive lines by means of vias which are etched through the insulating layers separating the levels. The vias are filled with metal to form via studs. These multiple levels of conductor wiring interconnection patterns, with the individual levels connected by via studs, operate to distribute signals among the circuits on the chip.
In its simplest form, a via may be formed by first masking an insulating layer with photoresist and then selectively etching a portion of the insulating layer. The via is etched through an opening formed in the photoresist using well known photolithographic techniques, to form an opening to the underlying conductive layer. Depending on the aspect ratio and the interconection ground rules, isotropic or anisotropic etching processes may be used to form a hole in the dielectric.
After the via etch, and photoresist removal, it is possible to deposit a conductive layer in the via. Conducting material is deposited in the via to form the electrical interconnect between the conducting layers. However, a liner layer is usually desirable between the insulating and conductive layers.
The presence of a liner layer on the sidewalls of the via is desirable because structural delamination and conductor metal diffusion can occur unless there is a layer of protection, a liner layer, between the conductive layer and the etched insulating layer. However, the best liner materials tend to be more resistive, as compared to conducting materials, so the presence of the liner at the bottom of the via increases the contact resistance of the structure. An increase in contact resistance is not desirable because it will lead to slower propagation of electrical signals through the wiring structure. For structural integrity, the liner layer should line the entire side wall and will generally cover the bottom of the via as well.
The liner and conductive layers may be deposited by sputtering, CVD, electroless deposition and electrodeposition. Rf bias sputtering, in general, is known in the art and involves the reemission of material during the sputter deposition thereof through the effects of attendant ion bombardment of the layer being deposited. In effect, Rf biased sputtering is the positive ion bombardment of a substrate or film during its deposition. Therefore, during Rf bias sputtering, there is always simultaneous etching and deposition of the material being deposited. Previously deposited layers are not etched as part of a standard Rf biased sputter deposition.
During Rf biased sputtering, particles are bombarded onto a target material so as to sputter the target material onto the semiconductor wafer substrate. During the process the ions being deposited also bombard the semiconductor substrate so that the substrate can have a smooth surface.
Materials capable of forming a liner layer generally have a higher resistance than conductive materials. Liner materials have generally been selected to simultaneously minimize contact resistance, provide adequate adhesion between insulative and conductive metal and provide a good diffusion barrier. The contact resistance problem is compounded when copper is used as the conductive metal. When copper is used, the presence of a continuous dissimilar liner material with comparatively higher resistivity at the bottom of the via deters the fabrication of a single crystalline, or continuous, interface between the via conductor material and the wiring level below. The formation of a single, crystalline interface is advantageous. The single crystalline structure provides greater structural integrity for the interface between the via and the wiring level below. For example, the deposition of a seed layer of copper prior to the electroplating of copper creates an environment that is more conducive to electroplating. The copper seed layer facilitates the formation of a single crystalline copper structure at the via-metal interface because the seed layer is structurally similar to the electroplated metal.
The prior art does not teach a method of selectively Rf biasing, during a sputter deposition, such that a deposited, liner layer is substantially removed from the bottom of the via while the deposited material on the sidewalls of the via is substantially unaffected. A method of providing such a structure is needed to facilitate the creation of continuous copper vias and conductive metal lines.
Thus there remains a need for a method of creating a via structure that is more conducive to electroless deposition and electrodeposition, especially copper electroplating; and a structure that has a liner material present on the sidewalls of the via but not the bottom of the via.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of forming a via with liner material on the sidewalls of the via but not the bottom of the via, i.e., a bottomless via.
It is another object of the present invention to provide a method of forming a bottomless via with a second material deposited on sidewalls of the via but not on the bottom of the via.
It is a further object of the present invention to provide an environment more conducive to the copper electroplating.
These and other features, aspects, and advantages will be more readily apparent and better understood from the following detailed description of the invention, which describes a method of forming a bottomless liner structure, comprising:
a) obtaining a material having a via;
b) depositing a first layer on the material having the via, the first layer covering the sidewalls and bottom of the via;
c) sputter depositing a second layer, the material Rf biased during at least a portion of the time that the second layer is sputter deposited, such that the first layer deposited on the bottom of the via is substantially removed and substantially all of the first layer deposited on the sidewalls of the via is unaffected.
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Revitz et.al. , Metallurgy Barrier for Au and Pb, IBM Technical Disclosure Bulletin, Apr. 1972.
Simon Andrew H.
Uzoh Cyprian E.
Ortiz Edgardo
RatnerPrestia
Ulrich, Esquire Lisa
Wilson Allan R.
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