Opamp and capacitor sharing scheme for low-power pipeline ADC

Details Opamp and capacitor sharing scheme for low-power pipeline ADC Opamp and capacitor sharing scheme for low-power pipeline ADC

2007-09-04

2007-09-04

Mai, Lam T. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S160000

Reexamination Certificate

active

11463813

ABSTRACT:
A first stage circuit for a high-speed, high-resolution pipeline analog-to-digital converter (ADC) implements operational amplifier (opamp) sharing and capacitor sharing to combine the sample-and-hold (SAH) and the MDAC (multiplying digital to analog converter) functions in the first residue stage of the pipeline ADC. In one embodiment, the first stage circuit includes a sampling capacitor, an amplifier, a feedback capacitor array and a comparator. The sampling capacitor and the feedback capacitor array are configured by switches to operate in a sampling/MDAC mode, a discharge mode and a hold mode. In this manner, the sample-and-hold operation and the MDAC operation are merged into the first stage circuit of the pipeline ADC to achieve low power and high speed of operation.

REFERENCES:
patent: 6724338 (2004-04-01), Min et al.
patent: 6954169 (2005-10-01), Min
patent: 7148833 (2006-12-01), Cho et al.
Iuri Mehr et al., “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” IEEE Journal of Solid-State Circuits, vol. 35, No. 3, Mar. 2000, pp. 318-325.
Byung-Moo Min et al., “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC,” IEEE Journal of Solid-State Circuits, vol. 38, No. 12, Dec. 2003, pp. 2031-2039.
Dan Kelly et al., “A 3V 340mW 14b 75MSPS CMOS ADC with 85dB SFDR at Nyquist,” 2001 IEEE International Solid-State Circuits Conference, 3 pages.

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