One word buffer memory system

Details One word buffer memory system One word buffer memory system

1979-07-27

1981-09-29

Atkinson, Charles E.

Boots, shoes, and leggings

364200, 365230, G06F 932, G11C 800

Patent

active

042926742

ABSTRACT:
A memory system which already includes an address register, a randomly accessible memory unit, a data-in register and a data-out register is converted to also include a one word buffer memory with the addition of only a few components. A plus one adder is included for incrementing the address contained in the address register and the result is then stored in an address plus one register. The randomly accessible memory unit may be accessed with the address plus one register when it has completed the normal access with the address register pending a new request. The resultant memory data from this access at the incremented address is stored in a one word internal register which is a buffer to the randomly accessible memory unit. Since such access is noninterfering with and overlapped in time with the overall memory system communication with a requestor, and pending any new request to the randomly accessible memory stores, it serves to efficiently create a buffer store only for the next consecutive address. When a new request from a requestor external to the memory system occurs, a comparator compares the new address as becomes lodged in the address register and the immediately previously requested address as is still temporarily lodged in the address plus one register. If they match, meaning that the next consecutive address has been referenced, referenced memory data word will already be available in the one word internal buffer register. If they do not match, the randomly accessible memory unit must be accessed in the normal manner.

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