One-transistor RAM approach for high density memory application

Details One-transistor RAM approach for high density memory application One-transistor RAM approach for high density memory application

2003-03-27

2003-12-09

Tsai, Jey (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

C438S244000, C438S248000, C257S301000

Reexamination Certificate

active

06661043

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to improve capacitor area efficiency in the creation of one-transistor RAM devices by using a 3-D structured capacitor.
(2) Description of the Prior Art
An important aspect of the creation of Dynamic Random Access Memory (DRAM) devices is the creation of the capacitive storage capability, whereby it is essential that storage node capacitor cell plates be large enough to retain an adequate voltage level without thereby being detrimentally affected by parasitic components of the structure or device noise that may be present during the operation of the device. Device performance improvements continue to be gained by reducing device dimensions, increasing the device density.
Typical DRAM storage cells are created comprising one single Metal-Oxide-Semiconductor Field-Effect-Transistor (MOS-FET) and a single capacitor, this DRAM storage cell is commonly referred to as a 1T-RAM device. The 1T-RAM device stores one bit of data on the capacitor as an electrical charge. Reductions in device dimensions and the therefrom following limitations in available surface area for the creation of the 1T-RAM capacitor create a serious obstacle to increasing the packing density of DRAM devices. The problem of maintaining storage capacity while at the same time decreasing the 1T-RAM device dimensions remain a serious challenge in creating high-density 1T-RAM devices.
Using a two-dimensional stacked capacitor for the creation of a 64 MB DRAM or 1T (planar) RAM cells, having a relatively small memory cell area does not allow for the creation of the required capacitive storage capability. To address this problem, stacked capacitors have been proposed that make use of a three-dimensional structure in order to improve storage capacity. Variations of the stacked capacitor are for instance double stack, fin-structured, cylindrical, spread stacked and box structured capacitors.
In more recent applications, the planar capacitor has found increased use since the planar capacitor offers the advantage of being fully compatible in its creation with conventional logic device creation processes. The 1-T RAM cell size is however difficult to reduce when using the planar capacitor. A number of solutions have been suggested for this problem, the invention provides such a solution that allows for the use of a planar capacitor without requiring a large amount of surface area for the there-with created 1T-RAM cell.
U.S. Pat. No. 5,918,148 (Sato) shows a one transistor (1T) SRAM process.
U.S. Pat. No. 5,434,438 (Kuo) shows a one transistor and one capacitor memory device.
U.S. Pat. No. 6,165,828 (Forbes) shows a process for a gated lateral transistor.
U.S. Pat. No. 6,143,636 (Forbes) discusses a flash memory process.
Leung, et al., “The ideal SoC Memory: 1T SRAM”, 0-7803-6598 4/00, IEEE pp. 32 to 36.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method that allows for the creation of a one-transistor DRAM device whereby emphasis is placed on improved capacitor area efficiency of the design.
In accordance with the objectives of the invention a new method is provided for the creation of a 1T RAM cell. Standard processing is applied to create STI trenches in the surface of a substrate, N
2
implantations are performed into the sidewalls of the STI trenches. A layer of lining oxide is created, the implanted N
2
interacts with the lining oxide to form SiON over exposed surfaces of the STI trenches. STI oxide is deposited and polished, filling the STI trenches there-with. Crown patterning is performed to define capacitor areas, the crown patterning stops on a layer of etch stop material and the created SiON and partially removes STI oxide from the STI trenches. Layers of etch stop material, exposed SiON and pad oxide are removed, exposing the surface of the silicon substrate, the etched layers of STI oxide are not affected by this removal. A layer of SAC oxide is grown, n-well and p-well implantations are performed into the surface of the substrate. The layer of SAC oxide is removed, gate oxide is grown, polysilicon is deposited and patterned and etched, forming polysilicon gate material and polysilicon top plate of the capacitor. Standard processing is further applied to complete the 1T-RAM cell by providing gate spacers and impurity implantations for the gate electrode, by saliciding contact surfaces and by providing contacts to the points of contact of the cell.


REFERENCES:
patent: 6348706 (2002-02-01), Sandhu
patent: 6486024 (2002-11-01), Tews et al.

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