One-transistor memory cell with enhanced capacitance

Details One-transistor memory cell with enhanced capacitance One-transistor memory cell with enhanced capacitance

1977-09-30

1979-07-31

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 24, 357 91, 365149, 365178, 365186, H01L 2704, G11C 1124

Patent

active

041632435

ABSTRACT:
A one-transistor memory cell is provided in which the depletion-layer capacitance of an MOS capacitor is increased by locally enhancing the substrate dopant concentration. In preferred embodiments the substrate may also be doped adjacent to the substrate-insulator boundary with ions of appropriate conductivity type to form a diode junction in the substrate. The effective capacitance of the memory cell is therefore the capacitance of the insulator in parallel with the substantially increased depletion-layer or diode junction capacitance.

REFERENCES:
patent: 3740731 (1973-06-01), Ohwada et al.
patent: 3740732 (1973-06-01), Frandon
patent: 4085498 (1978-04-01), Rideout
Tasch et al., IEEE Trans. on Electron Devices, vol. Ed 23, No. 2, Feb. 1976, pp. 126-131.
Abbas et al., IBM Tech. Discl. Bulletin, vol. 18, No. 10, Mar. 1976, p. 3288.

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