One transistor flash EPROM cell

Static information storage and retrieval – Floating gate – Particular biasing

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365218, G11C 1140

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active

049583212

ABSTRACT:
An electrically programmable floating gate transistor useful as a one transistor flash EPROM cell includes a multi-thickness dielectric provided on a substrate. The multi-thickness dielectric limits tunnelling from a floating gate provided on the multi-thickness dielectric to a drain during programming and allowing tunnelling from the floating gate to the source during erasing. The floating gate has a low doping concentration, less than 5.times.10.sup.18 cm.sup.-3, and a thickness of less than 1000 .ANG. to provide a self-limiting erase characteristic.

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"Flash-Erase EEPROM Cell with Asymmetric Source and Drain Structure", H. Kume et al., Central Research Laboratory, Hitachi, Ltd., IEEE IEDM 87, p. 560.
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