One-transistor dynamic ram with poly bit lines

Details One-transistor dynamic ram with poly bit lines One-transistor dynamic ram with poly bit lines

1979-08-20

1982-06-08

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

29571, 357 45, 357 68, 365149, 357 23, H01L 2710, H01L 2904, G11C 1140

Patent

active

043342361

ABSTRACT:
An MOS integrated semiconductor memory is disclosed with memory locations arranged in lines and columns. The memory locations in each case contain two one-transistor memory cells. For each memory location, two MOS transistors of the two one-transistor memory cells are controlled in common by means of a word line which runs in a line direction. The two MOS transistors are each coupled on a respective bit line which runs on one side of the memory locations in a column direction. Electrodes of the MOS memory capacitors and the gates of the MOS transistors of the one-transistor memory cells are formed by a first polysilicon layer and a second polysilicon layer, respectively. For reduction of area and also of bit line capacitance as well as at the same time raising the memory capacitance, the invention provides that the bit lines are provided as a third polysilicon layer forming polysilicon paths, and that the polysilicon paths which form the bit lines are coupled on only via limited doped connection zones in a semiconductor substrate which contains the memory cells of the MOS transistors.

REFERENCES:
patent: 4012757 (1977-03-01), Koo
patent: 4240195 (1980-12-01), Clemens et al.
Mitterer et al., "MOS-RAM . . . Doppel-Polysi . . . ", Elektronik-Anzeiger vol. 9, No. 7, Jul. 1977, pp. 19-22.
Fortino et al., IBM Technical Discl. Bulletin, vol. 20, No. 2, Jul. 1977, pp. 539-540.
Ho et al., IBM Technical Discl. Bulletin, vol. 20, No. 1, Jun. 1977, pp. 146-148.
Ahlquist et al., IEEE Int. Solid-State Circuits Conf., 1976, Digest of Technical papers, pp. 128-129, Feb. 1976.

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