One-transistor and one-capacitor DRAM cell for logic process...

Details One-transistor and one-capacitor DRAM cell for logic process... One-transistor and one-capacitor DRAM cell for logic process...

2000-03-28

2002-03-19

Elms, Richard (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S149000

Reexamination Certificate

active

06359802

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to dynamic random access memory (DRAM), and more specifically to a one-transistor and one-capacitor DRAM cell for logic process technology.
2. Description of the Related Art
The demand for quicker and more powerful personal computers has led to many technological advances in the computer industry, including combining logic devices and memory elements on the same integrated circuit. However, the technologies for logic devices and memory elements are diverging due to different requirements. Logic circuits need fast transistors and efficient connectivity and require extremely thin gate oxides and multiple metal layers. However, thin gate oxides create leakage problems for high-density memory elements. Presently, gate oxides are 15 Angstroms in thickness.
Higher memory bandwidth is driving the need for higher density memory elements with metal oxide semiconductor (MOS) diodes processed with logic technology. A dynamic random access memory cell with a thin gate oxide designed based on sub-micron logic technology has multiple leakage sources. The leakage sources are a) the sub-threshold drain to source leakage, b) the junction leakage, and c) the gate to substrate leakage. Memory cells require frequent refresh rates due to excessive leakage. The size of a capacitor is directly proportional to the amount of charge stored in the capacitor. However, a larger capacitor results in higher gate to substrate leakage since the leakage is proportional to the area of the MOS thin gate oxide diode capacitor.
MOS capacitors have different values depending on the state of the semiconductor surface. An accumulation layer is formed when the gate to substrate voltage (Vgs) is less than 0 for a p-substrate structure. The MOS capacitor operates as a parallel-plate capacitor if an accumulation layer is present, where the gate is one plate of the capacitor and the high concentration of holes in a p-substrate is the other plate of the capacitor. A depletion layer is formed under the gate by applying a slightly positive voltage Vgs. The positive voltage repels holes and forms a negatively charged layer depleted of carriers. As gate to substrate voltage (Vgs) further increases, minority carriers are attracted to the surface and invert the silicon to form a n-type layer or channel.
Similarly, with a n-substrate structure, if Vgs is greater than zero the surface is in the accumulation mode and the gate layer acts a plate of the capacitor while the substrate acts as the second plate of the capacitor. Applying a small negative Vgs forms a depletion layer. An inversion layer is formed at the surface by utilizing a larger negative Vgs. However, transistors operating in inversion mode with thin gate oxides have high gate to substrate leakage.


REFERENCES:
patent: 5694355 (1997-12-01), Skjaveland et al.
patent: 5870329 (1999-02-01), Foss
patent: 5943270 (1999-08-01), Borkar
patent: 6075720 (2000-06-01), Leung et al.
Foss, Richard C., “Implementing Application Specific Memory,” 1996 IEEE International Solid-State Circuits Conference, Technology Directions: Memory, Paper FP 16.1, 2 pages, Feb. 1996.
Gillingham, et al., “A 768k Embedded DRAM for 1.244Gb/s ATM Switch in a 0.8&mgr;m Logic Process,” 1996 IEEE ISSCC Technology Directions: Memory, Paper FP 16.2, 2 pages, Feb. 1996.

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