One-time programming multiple-level memory cells

Details One-time programming multiple-level memory cells One-time programming multiple-level memory cells

2006-02-21

2006-02-21

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read only systems

Resistive

C365S159000, C365S148000, C365S071000

Reexamination Certificate

active

07002832

ABSTRACT:
A multiple-level memory cell including a storage element formed of several polysilicon resistors connected in series between two input/output terminals; and a load in series with said resistive element, the midpoint of this series connection forming a read terminal of the memory cell, and the respective junction points of said resistors of the storage element being accessible.

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Kato K. et al. “A Physical Mechanism of Current-Induced Resistance Decrease In Heavily Doped Polysilicon Resistors” IEEE Transactions on Electron Devices, IEEE Inc. New York, US, vol. 29, No. 8, Aug. 1982, pp. 1156-1161.

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