Static information storage and retrieval – Read only systems – Fusible
Reexamination Certificate
2000-02-24
2001-03-27
Mai, Son (Department: 2818)
Static information storage and retrieval
Read only systems
Fusible
C365S225700, C365S208000, C327S525000
Reexamination Certificate
active
06208549
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to a polycide fuse memory array architecture for standard sub 0.35 micron processes.
2. Description of the Related Art
Most integrated circuits (“chips”) now in use are fabricated in what is called CMOS (complementary metal oxide semiconductor) technology, which forms both PMOS and NMOS transistors in a silicon substrate. One of the main objectives of integrated circuit technology is to minimize transistor size. Typically, transistors are described in terms of their minimum feature dimension. Current technology provides a minimum feature size of 0.35 &mgr;m or less. The minimum feature size, which is also referred to as a “line width”, refers to the minimum width of a transistor feature such as the gate width, or the separation between source and drain diffusions. Typically, 0.35 &mgr;m technology is used to form CMOS transistors having a gate oxide thickness of 70 Å. A 0.18 &mgr;m technology is used to form CMOS transistors having a gate oxide thickness of 40 Å. The gate “oxide”, actually a silicon dioxide layer, is the electrically insulating (dielectric) layer interposed between the conductive gate electrode, which is typically a polycrystalline silicon structure formed overlying the principal surface of the silicon substrate in which the integrated circuit is formed, and the underlying silicon which typically is the channel portion of the transistor extending between the source and drain regions. Transistors of 0.35 &mgr;m size typically operate at a voltage of 3.3 Volts. Transistors of 0.18 &mgr;m size typically operate at a voltage of 1.8 Volts. Greater voltages are likely to destroy the transistor by rupturing the gate oxide.
A chip fabricated using a 0.18 micron process typically includes core circuitry having transistors of a 0.18 micron size, and input/output circuitry having transistors of a 0.35 micron size. Consequently, 1.8 Volts is used to run the core circuitry of the chip, and 3.3 Volts is used to run the input/output circuitry of the chip. Such a configuration facilitates interfacing the chip to other 3.3 Volt chips. The voltage used to run the input/output circuitry of the chip is designated as the input/output supply voltage, V
IO
.
In the field of data storage, there are two main types of storage elements. The first type is a volatile storage element such as typically used in DRAM (dynamic random access memory) or SRAM (static random access memory) in which the information stored in a particular storage element is lost the instant that power is removed from the circuit. The second type is a non-volatile storage element in which the information is preserved even if power is removed. Typically, the types of devices used to provide non-volatile storage are substantially different from those used in ordinary logic circuitry or in volatile storage, thereby requiring different fabrication techniques.
Non-volatile fuse elements have been fabricated using a standard CMOS process. Non-volatile fuse elements are described in U.S. Pat. No. 5,708,291 to Bohr et al., U.S. Pat. No. 5,066,998 to Fischer et al., “Comparison of Transformation to Low-Resistivity Phase and Agglomeration of TiSi
2
and CoSi
2
” by Lasky et al, IEEE Transactions on Electron Devices, pp. 262-269, Vol. 38, No. 2, February 1991, and “A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process” by Alavi et al., IEDM 1997, pp. 855-858. However, these references fail to teach an adequate method of using these fuse elements in an array.
It would therefore be desirable to provide an array of non-volatile fuse elements on an integrated circuit chip formed exclusively using a standard CMOS processes.
SUMMARY
Accordingly, the present invention provides a non-volatile fuse-based memory array, which is fabricated using a standard sub 0.35 micron CMOS process. In one embodiment, the non-volatile memory circuit is fabricated using a standard 0.18 micron CMOS process. The core transistors fabricated in accordance with the 0.18 micron &mgr;m CMOS process have a gate oxide thickness of 40 Å, and are designed to operate in response to a nominal supply voltage of 1.8 Volts. The 0.18 micron CMOS process also provides for the fabrication of high voltage CMOS transistors that have a gate oxide thickness of 70 Å. These high voltage CMOS transistors are typically used in the input/output (I/O) circuitry of the integrated circuit chip.
The non-volatile memory array of the present invention includes a non-volatile memory cell that uses a polycide fuse as the storage device. The polycide fuse (i.e., polycide resistor) is fabricated using a sub 0.35 micron CMOS process. The polycide fuse includes a polysilicon structure having a width equal to the width of a gate electrode in the sub 0.35 micron process (i.e., a gate of the standard CMOS process). A thin layer of titanium silicide is formed over the polysilicon structure to reduce the resistance of the resulting polycide fuse structure. An access control circuit is provided to pass a high current of approximately 5 mA through the polycide resistor, thereby heating the titanium silicide to a level, which causes the polycide fuse to become discontinuous. After programming, the resistance of the polycide fuse is increased by about one order of magnitude. The access control circuit is operated in response to both the V
IO
supply voltage and the V
DD
supply voltage.
The state of the polysilicon resistor is read through the access control circuit by comparing the resistance of the polycide fuse with a known, predetermined resistance. In one embodiment, the predetermined resistance has a value greater than the resistance of the unprogrammed polycide fuse, and less than the resistance of the programmed polycide fuse.
The present invention also includes a structure for accessing an array of polycide fuses. This structure includes a single access control circuit configured to individually program and read each of the polycide fuses in the array. Row and column decoding circuits are provided to selectively connect one of the polycide fuses to the access control circuit in response to an address signal. In one embodiment, the access control circuit includes a partial sense amplifier circuit. This partial sense amplifier circuit is completed when the row and column decoding circuits connect one of the polycide fuses to the partial sense amplifier circuit. The completed sense amplifier circuit compares the resistance of the connected polycide fuse with a reference resistance to determine the state of the polycide fuse. The completed sense amplifier circuit provides an output signal representative of the state of the connected polycide fuse.
The access control circuit also includes a high-voltage programming transistor connected between the V
IO
supply terminal and the partial sense amplifier circuit. When the programming transistor is turned on, the V
IO
supply voltage is applied to the connected polycide fuse. Under these conditions, the connected polycide fuse is programmed.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5066998 (1991-11-01), Fischer et al.
patent: 5708291 (1998-01-01), Bohr et al.
patent: 5812477 (1998-09-01), Casper et al.
patent: 5844298 (1998-12-01), Smith et al.
patent: 5936880 (1999-08-01), Payne
patent: 5999038 (1999-12-01), Pathak et al.
Jerome B. Lasky, James S. Nakos, Orison J. Cain, and Peter J. Geiss, “Comparison of Transformation to Low-Resistivity Phase and Agglomeration of TiSi2and CoSi2”, IEEE Transactions on Electron Devices, vol. 38, No. 2, Feb. 1991, pp. 262-269.
Mohsen Alavi, Mark Bohr, Jeff Hicks, Martin Denham, Allen Cassens, Dave Douglas, Min-Chun Tsai, “A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process”, IEEE 1977, pp. 34.3.1-34.3.4.
Rao Kameswara K.
Voogel Martin L.
Bever Hoffman & Harms LLP
Cartier Lois D.
Hoffman E. Eric
Mai Son
Xilinx , Inc.
LandOfFree
One-time programmable poly-fuse circuit for implementing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with One-time programmable poly-fuse circuit for implementing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and One-time programmable poly-fuse circuit for implementing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2483900