Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-09-28
2003-06-17
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S530000, C438S600000, C438S601000
Reexamination Certificate
active
06580144
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to programmable memory cells. More particularly, the invention relates to a one-time programmable memory cells.
BACKGROUND OF THE INVENTION
The demand for semiconductor devices has increased dramatically in recent years. One can readily observe the pervasiveness of consumer electronic devices in the modern world. Most or all of the consumer electronic devices are made possible because of developments in semiconductor devices. As the consumer electronic devices become smaller, more sophisticated, and less expensive, increasingly higher densities of the semiconductor devices, including memories, are demanded at a lower cost in today's market place.
In the field of memories, the demand for ever increasing densities and lower cost is particularly true, especially for the non-volatile memories, i.e., those memories that do not lose data even when power is not supplied.
A non-volatile memory may be a one time programmable (“OTP”) or reprogrammable. As the name suggests, OTP memory is programmed once, and it is permanent for all practical purposes. Most OTP memories can be categorized into four basic types: 1) anti-fuse, 2) fuse, 3) charge storage (EPROM), and 4) mask ROM.
Existing OTP memory technologies described above are based on cell sizes considerably larger than 4&lgr;
2
, the minimum cell size for a cross-point memory. In addition, in each case the memory cell consists of a single plane of memory elements constructed on a single crystal silicon substrate, with sense and programming electronics located around the periphery of the memory array. Since single crystal silicon transistors are integral components of the memory elements in the foregoing technologies, stacking memory layers on top of one another to increase density is not possible. Consequently, high density, low cost OTP memories are difficult to fabricate.
SUMMARY OF THE INVENTION
In one respect, an exemplary embodiment of a memory cell may include a top conductor extending in a first direction and a bottom conductor extending in a second direction. The top and bottom conductors define a region of overlap at an intersection between the two conductors. The top and bottom conductors are electrically connected. The memory cell may also include a fuse formed in the region of overlap between the top and bottom conductors. The fuse may also have electrical connectivity with the top and bottom conductors. Further, the memory cell may include an anti-fuse in electrical series with the fuse. The anti-fuse may also be formed between the top and bottom conductors. The fuse may be vertically oriented, i.e. the current substantially flows vertically within the fuse.
In another respect, an exemplary embodiment of a method of fabricating a memory cell may include forming a top conductor extending in a first direction and forming a bottom conductor extending in a second direction so as to define a region of overlap at an intersection between the top and bottom conductors. The top and bottom conductors may have electrical connectivity with each other. The method may also included forming a fuse in the cross-point between the top and bottom conductors. The method may further include forming an anti-fuse in electrical series with the fuse.
The above disclosed exemplary embodiments may be capable of achieving certain aspects. For example, the size of the memory cell may be dramatically reduced. This enables providing a high density OTP memory cell at much lower cost. Also, the memory cell may be fabricated using standard semiconductor processes and materials, and thus, little to no capital investment may be required beyond that present in the current state-of-the-art manufacturing. Further, the current flow in the memory cells is substantially perpendicular (vertical) to the substrate plane. This allows the cells to be inserted between adjacent conductors. In particular, the cells can be placed at an intersection of a cross-point array of conductors to form a cross-point OTP memory array. The cross-point memory arrays can be fabricated such that the planar area of each memory cell is 4&lgr;
2
. Planes of these arrays can be stacked on top of one another, which increases the density dramatically.
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Hewlett--Packard Development Company, L.P.
Le Thao X.
Ngo Ngan V.
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