Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-05-07
2003-06-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S253000, C438S396000
Reexamination Certificate
active
06576482
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuit processing, and more particularly relates to a method of manufacturing an FeRAM.
BACKGROUND OF THE INVENTION
The semiconductor industry has long faced a demand for small, portable personal devices. These devices include cellular phones, personal computing equipment, and personal sound systems, which are sought in continuously smaller sizes and with continuously lower power requirements. At the same time that smaller and more portable personal devices are sought, computational power and on-chip memory requirements are increasing. In light of these requirements, there has been a long-felt need for computational devices that have substantial memory and logic functions integrated within individual semiconductor chips. Preferably, the memory is configured such that if power is interrupted, as when a battery fails, the contents of the memory are retained. Memory that retains its content without a continuous supply of power is called non-volatile memory. Conventional non-volatile memory types include: electrically erasable, programmable read only memory (EEPPROM) and flash EEPROM.
Ferroelectric random access memory (FeRAM) is a type of non-volatile memory that stores data in memory cells that include capacitors employing a ferroelectric material, such as SBT or PZT, as the dielectric. The non-volatility of FeRAMs results from the bi-stable characteristic of ferroelectric materials. At least two types of ferroelectric memory cells are used, single capacitor memory cells and dual capacitor memory cells. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area and thereby increases the potential density of the memory array, but is less immune to noise and process variations. A 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area and stores complementary signals allowing differential sampling of the stored information. The 2C memory cell is more stable than the 1C memory cell.
As illustrated in prior art
FIG. 1
, a 1T/1C FeRAM cell
100
includes a transistor
110
and a ferroelectric storage capacitor
120
. The transistor
110
includes a gate
112
, a source
114
, and a drain
116
. The storage capacitor
120
includes a bottom electrode
122
, a top electrode
124
, and a ferroelectric core. The drain
116
of the transistor
110
is connected to the bottom electrode
122
of the capacitor
120
. The source
114
of the transistor
110
is connected to a bit line
132
(BL). The 1T/1C cell
100
is read by a pplying a signal to the gate
112
through a word line
130
(WL), switching on the transistor
110
. This brings the bottom electrode
122
of the capacitor
120
into communication with the bit line
132
. Then, though a drive line
134
(DL), a pulse signal is applied to the top electrode
124
of the capacitor
120
. The potential on the bit line
132
becomes the capacitor charge divided by the bit line capacitance. Since the capacitor charge is dependent upon the bi-stable polarization state of the ferroelectric core, the bit line potential can have two distinct values. A sense amplifier (not shown) is connected to the bit line
132
and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bit line that is not being read. In this manner, the data stored in the 1T/1C cell
100
is retrieved.
A characteristic of the cell
100
is that read operations are destructive. After a read operation, the data is rewritten to restore its value. This is similar to the way a DRAM operates. A difference from a DRAM, however, is that the ferroelectric memory cell retains its state until it is interrogated, thereby eliminating the need for refresh.
Prior art
FIG. 2
, illustrates a 2T /2C memory cell
200
. The memory cell
200
comprises two transistors
202
and
204
and two ferroelectric capacitors
206
and
208
, respectively. The first transistor
202
couples between a bit line
210
and the first capacitor
206
. The second transistor
204
couples between a bit line-bar
212
and the second capacitor
208
. The capacitors
206
and
208
are connected to a common drive line
214
(DL), to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors
202
and
204
of the dual capacitor ferroelectric memory cell
200
are enabled via a word line
216
(WL) to couple the capacitors
206
and
208
to the complementary logic levels on the bit line
210
and the bit-bar line
212
. The common drive line
214
of the capacitors is pulsed during the write operation to polarize the dual capacitor memory cell
200
to one of two logic states.
In a read operation, the first and second transistors
202
and
204
are enabled via the word line
216
to couple the information stored on the first and second capacitors
206
and
208
to the bit line
210
and the bit line-bar line
212
, respectively. A differential signal (not shown) is thus generated across the bit line
210
and the bit line-bar line
212
. A sense amplifier (not shown) senses the differential signal and determines the logic level stored in memory.
Forming devices with FeRAM presents several challenges. The ferroelectric capacitor alone requires many separate layers. In addition to the ferroelectric material and top and bottom electrode layers, diffusion barrier layers are generally required between the bottom electrode and the plug that contacts the transistor drain and between the top electrode and the upper contact. The electrodes themselves are often provided in two layers to address resistance requirements and material compatibility requirements. These various layers comprising diverse materials must all be deposited and etched without causing contamination between the various structures of the semiconductor device. It is also desirable to limit the number and complexity of processing steps. In view of these challenges, there has been a long felt need for improved FeRAM manufacturing processes.
SUMMARY OF THE INVENTION
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to a processing method useful in the formation of an FeRAM having a transition metal aluminum nitride upper diffusion barrier layer. The method provides a one-step process for forming a transition metal aluminum oxynitride layer over a transition metal aluminum nitride layer. The transition metal aluminum oxynitride layer can serve as a hard mask layer and can also become part of the upper diffusion barrier layer. According to the invention, a transition metal aluminum nitride layer is sputter deposited using a transition metal/aluminum target in an atmosphere containing nitrogen. Subsequently, the oxygen content of the atmosphere is increased, whereby a transition metal aluminum oxynitride layer is deposited without otherwise reconditioning the target. The invention eliminates the need to interrupt processing while conditioning the target with oxygen or replacing the target, thus making into a one-step process a deposition of layers previously thought to require a two-step process. A top electrode, such as an lr/lrO electrode, can also be deposited as part of the one-step process.
According to another aspect of the invention, a transition metal aluminum nitride layer is sputter-deposited over a transition metal aluminum oxynitride layer by reducin
Aggarwal Sanjeev
Hunter Stevan G.
Summerfelt Scott R.
Brady III W. James
Garner Jacqueline J.
Kennedy Jennifer M.
Niebling John F.
Telecky , Jr. Frederick J.
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