One-shot signal generating circuit

Details One-shot signal generating circuit One-shot signal generating circuit

2002-09-10

2003-11-11

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189110, C365S233100

Reexamination Certificate

active

06646956

ABSTRACT:

TECHNICAL FIELD
This invention relates to a one-shot signal generation circuit which generates a one-shot signal for determining the internal operational timing of an asynchronous memory.
BACKGROUND ART
As a conventional asynchronous memory, there has been a memory which operates by generating a one-shot signal internally when an external address has changed. As a one-shot signal generation circuit for generating this one-shot signal, generally a circuit as shown in
FIG. 19
is employed. The one-shot signal generation circuit shown in this figure detects change (transition) of address signals A
0
-AX which are its input signals, generates a plurality of address transition detection signals (hereinafter termed ATD signals) in pulse form, and combines these ATD signals into a single one-shot signal. Various internal signals for providing timing for internal operations, such as latch signals for latching addresses, are generated from the one-shot signal which has been generated in this manner.
The structure of a one-shot signal generation circuit according to the background art will be explained in the following in concrete terms. In
FIG. 19
, the reference symbols
5
-
0
to
5
-X denote address transition detection circuits (ATD
0
-ATDX). These address transition detection circuits
5
-
0
to
5
-X detect transitions of address signals A
0
-AX, and generate ATD signals having pulse widths greater than the skew widths which these address signals A
0
-AX have. The reference symbol
6
denotes a NOR gate (a negative logical sum gate circuit). This NOR gate
6
combines the plurality of ATD signal output from the address transition detection circuits
5
-
0
to
5
-X into a single signal S
6
(a pulse signal).
The reference symbol
7
denotes a predetermined number (an odd number) of inverter gates connected together as a cascade, and the reference symbol
8
is a NOR gate. In this example, the inverter gates
7
and the NOR gate
8
constitute an edge detection circuit which detects the low edge of the output signal S
6
of the NOR gate
6
, and, when the low edge is input, a one-shot signal S
8
is output which has a pulse width corresponding to the delay time of the inverter gates
7
. These inverter gates
7
and the NOR gate
8
function as a timing adjustment circuit for adjusting the timing of the output signal of the NOR gate
6
, and they adjust the pulse width of the one-shot signal which is output from the NOR gate
6
to a pulse width which corresponds to the delay time provided by the inverter gates
7
.
According to this background art circuit structure, after the arriving address signals A
0
, A
1
. . . , AX which have skew have been subjected by the address transition detection circuits (ATD
0
-ATDX)
5
-
0
,
5
-
1
to
5
-X to waveform shaping into ATD signals (the output signals of the address transition detection circuits
5
-
0
to
5
-X) which have pulse widths greater than the skew widths of the address signals, these signals are combined by the NOR gate
6
into a single signal. Accordingly, the output signal of this NOR gate
6
has a pulse width greater than the skew widths of the address signals A
0
, A
1
-AX. The timing adjustment circuit which is made up from the inverter gates
7
and the NOR gate
8
adjusts the timing of the output signal of the NOR gate
6
, and generates the one-shot signal S
8
which has a predetermined pulse width.
FIG. 20
shows the address transition detection circuit (ATD
0
)
5
-
0
. The structures of the other address transition detection circuits (ATD
1
-ATDX)
5
-
1
to
5
-X are the same as that shown in FIG.
20
.
In
FIG. 20
, the reference symbol
170
denotes a delay circuit, the reference symbol
171
denotes an inverter, and the reference symbols
173
,
174
, and
175
denote NAND gates (negative logical product gates). Here, along with the input signal (the address signal A
0
) being delayed by the delay circuit
170
and becoming one of the input signals to the NAND gate
173
, also it is inverted by the inverter
171
and, in the same manner, becomes the other input signal to the NAND gate
173
. The delay circuit
170
, inverter
171
, and NAND gate
173
constitute a circuit system which detects the fact that the input signal has undergone a transition from high level to low level.
Furthermore, along with the input signal (the address signal A
0
) being delayed by the delay circuit
170
and becoming one of the input signals to the NAND gate
174
, also it becomes the other input signal to this NAND gate
173
. This delay circuit
170
and NAND gate
174
constitute a circuit system which detects the fact that the input signal has undergone a transition from low level to high level. The NAND gate
175
combines the pulse signals output from the NAND gate
173
and the NAND gate
174
into a single signal. In this example, when the input signal has undergone a transition, one or the other of the NAND gate
173
and the NAND gate
174
outputs a pulse signal at low level, according to the direction of this transition. The NAND gate
175
receives these pulse signals and outputs the ATD signal. The pulse width of this ATD signal is determined by the delay time of the delay circuit
170
.
For the delay circuit
170
which is used in the address transition detection circuit, there are the circuit type shown in FIG.
21
and the circuit type shown in FIG.
22
. The circuit type of
FIG. 21
is a delay circuit in which a plurality of inverter gates
180
are connected as a cascade, and it provides the desired delay time by accumulating the operational delay time of each of the inverters. Furthermore, the circuit type of
FIG. 22
is a delay circuit in which a capacitor
191
is connected to each stage of inverter gates
190
which are connected as a cascade, and it provides the desired delay time by delaying the output signals of the respective inverters with the capacitors
191
. The delay time of this delay circuit
170
is set to a value which is greater than the skew width of the address signal.
As has been explained above, according to the background art, since the pulse widths of the ATD signals which are respectively output from the address transition detection circuits
5
-
0
,
5
-
1
to
5
-X are greater than the skews of the address signals A
0
, A
1
-AX, the one-shot signal which is output from the NOR gate
8
is not separated into a plurality of pulse signals even due to the input of address signals A
0
, A
1
-AX which arrive having skew, but is generated as a single pulse signal.
However, with the address transition detection circuits according to the background art, problems occur like the following due to the use of various types of delay circuit such as the delay circuit
170
for determining the pulse width of the ATD signal and the inverter gates
7
for timing adjustment and so on.
(1) Increase of Current Consumption by the Delay Circuit
Among the circuit systems for the delay circuit
170
which makes up the address transition detection circuit, according to the circuit system shown in
FIG. 21
, a large number of inverter gates of high drive power connected in a cascade are required for each of a plurality of ATD signals (for each address transition detection circuit). Accordingly, with this circuit system, there are the problems that the occupancy area upon the chip becomes large, and moreover the power consumption is increased by the activation of the large number of inverter gates of high drive power.
(2) Variation in the Delay Time of the Delay Circuit
The circuit system shown in
FIG. 22
is made by connecting inverter gates whose drive power is small in a cascade, and it generates its delay time by driving each of capacitors with each of the inverter gates. Here, variations in the drive power of the inverter gates come to exert a great influence upon the delay time when the number of stages of the inverter gates is increased, since the amounts of variation in the drive power of the inverter gates are superposed. Furthermore, the smaller are the transistors in gate width and gate lengt

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