One-shot pulse synchronizer

Details One-shot pulse synchronizer One-shot pulse synchronizer

1999-06-08

2001-04-17

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S146000, C327S172000, C327S144000

Reexamination Certificate

active

06218874

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to synchronizing circuits generally and, more particularly, to a circuit and/or method that may synchronize a one-shot pulse signal to a different clock domain.
BACKGROUND OF THE INVENTION
A conventional implementation of a synchronizer
10
involves the utilization of a flip-flop
12
and a flip-flop
14
in a cascaded configuration, as shown in FIG.
1
. The flip-flops
12
and
14
attempt to reduce the probability of metastable behavior of the synchronized signal. For the cases when the frequency of the input clock signal is higher than that of the output clock signal, there is a risk that short input pulses may be missed by the flip-flop
12
, thus being filtered by the synchronization logic.
Some of the undesirable behavior of the synchronizer
10
of
FIG. 1
can be avoided by implementing an SR flip-flop in the input clock domain, along with additional feedback logic.
FIG. 2
illustrates such an architecture
20
including a one-shot state machine
22
, a double synchronizer
24
, a double synchronizer
26
and a SR flip-flop
28
. The SR flip-flop
28
and the double synchronizer
24
are clocked by a signal CLOCK_IN. The double synchronizer
26
is clocked by a signal CLOCK_OUT. The double synchronizers
24
and
26
can each contain the circuitry of the synchronizer
10
of FIG.
1
and are implemented in both the feed-forward and feedback paths.
The circuit
20
has a high latency and recovery time due to the implementation of the two double synchronizers
24
and
26
. In addition, the circuit
20
requires a relatively large number of storage elements, which increases the implementation area and overall power consumed.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a memory section and a first circuit. The memory section may be configured to present a first output in response to (i) a first clock signal, (ii) a second clock signal, (iii) an input pulse and (iv) the first output. The first circuit may be configured to generate a second output in response to (i) the first output and (ii) the second clock signal, where the second output may comprise a pulse having a width equal to a period of the second clock signal. In one example, an input circuit may be configured to present the first output to the memory section in response to the input pulse and a first feedback of the output.
The objects, features and advantages of the present invention include providing a synchronizing circuit that may (i) reliably capture and report a one-shot pulse signal generated in a different clock domain, (ii) minimize the latency (or propagation delay) of the pulse signal through the synchronizing circuit by reducing the number of flip-flops in the forward path, (iii) maximize the rate at which the incoming pulses may arrive and still be able to be captured, (iv) minimize the number of elements required for the implementation, (v) provide an implementation that may be easily tested, (vi) eliminate synchronization logic in the is feedback path, (vii) reduce recovery time, (viii) be implemented without a clock and/or asynchronous reset signal gating, and/or (ix) be implemented with a minimum number of flip-flops.


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patent: 5-206797 (1993-08-01), None

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